yul/CANOpen_OMG
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yul
2022-06-21 16:11:21 +02:00
commit 145517c15f
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################################################################################
# Automatically-generated file. Do not edit!
################################################################################
-include ../makefile.init
RM := rm -rf
# All of the sources participating in the build are defined here
-include sources.mk
-include src/subdir.mk
-include subdir.mk
-include objects.mk
ifneq ($(MAKECMDGOALS),clean)
ifneq ($(strip $(C_DEPS)),)
-include $(C_DEPS)
endif
endif
-include ../makefile.defs
OPTIONAL_TOOL_DEPS := \
$(wildcard ../makefile.defs) \
$(wildcard ../makefile.init) \
$(wildcard ../makefile.targets) \
BUILD_ARTIFACT_NAME := CANOpen_attempt
BUILD_ARTIFACT_EXTENSION := axf
BUILD_ARTIFACT_PREFIX :=
BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),)
# Add inputs and outputs from these tool invocations to the build variables
# All Target
all:
+@$(MAKE) --no-print-directory main-build && $(MAKE) --no-print-directory post-build
# Main-build Target
main-build: CANOpen_attempt.axf
# Tool invocations
CANOpen_attempt.axf: $(OBJS) $(USER_OBJS) makefile objects.mk $(OPTIONAL_TOOL_DEPS)
@echo 'Building target: $@'
@echo 'Invoking: MCU Linker'
arm-none-eabi-gcc -nostdlib -L"/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/Debug" -Xlinker -Map="CANOpen_attempt.map" -Xlinker --cref -Xlinker --gc-sections -Xlinker -print-memory-usage -mcpu=cortex-m3 -mthumb -T "uart2can-bin_bla_Debug.ld" -o "CANOpen_attempt.axf" $(OBJS) $(USER_OBJS) $(LIBS)
@echo 'Finished building target: $@'
@echo ' '
# Other Targets
clean:
-$(RM) $(EXECUTABLES)$(OBJS)$(C_DEPS) CANOpen_attempt.axf
-@echo ' '
post-build:
-@echo 'Performing post-build steps'
-arm-none-eabi-size "CANOpen_attempt.axf"; # arm-none-eabi-objcopy -v -O binary "CANOpen_attempt.axf" "CANOpen_attempt.bin" ; # checksum -p LPC1769 -d "CANOpen_attempt.bin";
-@echo ' '
.PHONY: all clean dependents post-build
-include ../makefile.targets

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################################################################################
# Automatically-generated file. Do not edit!
################################################################################
USER_OBJS :=
LIBS := -lCMSIS_CORE_LPC17xx

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################################################################################
# Automatically-generated file. Do not edit!
################################################################################
OBJ_SRCS :=
S_SRCS :=
ASM_SRCS :=
C_SRCS :=
S_UPPER_SRCS :=
O_SRCS :=
EXECUTABLES :=
OBJS :=
C_DEPS :=
# Every subdirectory with source files must be described here
SUBDIRS := \
src \

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src/accelo.o src/accelo.d: ../src/accelo.c ../src/accelo.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/LPC17xx.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cm3.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmInstr.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmFunc.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h \
../src/i2c.h
../src/accelo.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/LPC17xx.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cm3.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmInstr.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmFunc.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h:
../src/i2c.h:

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../src/accelo.c:10:8:convert_to_gravity_scale_2g 32 static
../src/accelo.c:17:5:transform_from_two_compli 32 static
../src/accelo.c:41:6:setCtrl 8 static
../src/accelo.c:53:6:read_one_set_data 160 static
../src/accelo.c:82:6:get_one_set_data 136 static

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src/callback.o src/callback.d: ../src/callback.c \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/LPC17xx.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cm3.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmInstr.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmFunc.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h \
../src/callback.h
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/LPC17xx.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cm3.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmInstr.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmFunc.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h:
../src/callback.h:

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../src/callback.c:17:6:callback_add 16 static
../src/callback.c:25:6:callback_setflag 24 static
../src/callback.c:35:6:callback_do 16 static

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src/can.o src/can.d: ../src/can.c ../src/can.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/LPC17xx.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cm3.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmInstr.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmFunc.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h
../src/can.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/LPC17xx.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cm3.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmInstr.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmFunc.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h:

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/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cm3.h:1323:22:NVIC_EnableIRQ 16 static
../src/can.c:21:6:can_config 8 static
../src/can.c:48:6:can_send 40 static
../src/can.c:85:6:can_receive 24 static
../src/can.c:102:6:can_sdo_send 24 static
../src/can.c:122:6:can_sdo_receive 16 static

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src/cr_startup_lpc175x_6x.o src/cr_startup_lpc175x_6x.d: \
../src/cr_startup_lpc175x_6x.c

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../src/cr_startup_lpc175x_6x.c:222:6:data_init 40 static
../src/cr_startup_lpc175x_6x.c:231:6:bss_init 24 static
../src/cr_startup_lpc175x_6x.c:257:1:ResetISR 24 static
../src/cr_startup_lpc175x_6x.c:314:6:NMI_Handler 4 static
../src/cr_startup_lpc175x_6x.c:319:6:HardFault_Handler 4 static
../src/cr_startup_lpc175x_6x.c:324:6:MemManage_Handler 4 static
../src/cr_startup_lpc175x_6x.c:329:6:BusFault_Handler 4 static
../src/cr_startup_lpc175x_6x.c:334:6:UsageFault_Handler 4 static
../src/cr_startup_lpc175x_6x.c:339:6:SVC_Handler 4 static
../src/cr_startup_lpc175x_6x.c:344:6:DebugMon_Handler 4 static
../src/cr_startup_lpc175x_6x.c:349:6:PendSV_Handler 4 static
../src/cr_startup_lpc175x_6x.c:354:6:SysTick_Handler 4 static
../src/cr_startup_lpc175x_6x.c:365:6:IntDefaultHandler 4 static

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src/crp.o src/crp.d: ../src/crp.c

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src/i2c.o src/i2c.d: ../src/i2c.c ../src/i2c.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/LPC17xx.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cm3.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmInstr.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmFunc.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h \
../src/callback.h
../src/i2c.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/LPC17xx.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cm3.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmInstr.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmFunc.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h:
../src/callback.h:

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/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cm3.h:1323:22:NVIC_EnableIRQ 16 static
../src/i2c.c:18:6:i2c_start_transaction 4 static
../src/i2c.c:22:6:I2C0_IRQHandler 8 static
../src/i2c.c:120:6:i2c_write_register 16 static
../src/i2c.c:134:6:i2c_read_registers 32 static
../src/i2c.c:148:9:i2c_read_register 24 static
../src/i2c.c:158:6:i2c_init 8 static
../src/i2c.c:175:6:i2c_transact 4 static

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src/lcd.o src/lcd.d: ../src/lcd.c \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/LPC17xx.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cm3.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmInstr.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmFunc.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h \
../src/lcd.h ../src/ssp.h
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/LPC17xx.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cm3.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmInstr.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmFunc.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h:
../src/lcd.h:
../src/ssp.h:

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../src/lcd.c:8:6:Delay 24 static
../src/lcd.c:15:6:Write_Cmd 24 static
../src/lcd.c:22:6:Write_Cmd_Data 24 static
../src/lcd.c:28:6:disp_setwindow 32 static
../src/lcd.c:54:6:disp_clear 32 static
../src/lcd.c:71:6:disp_setpix 32 static
../src/lcd.c:83:6:disp_chunk 40 static
../src/lcd.c:116:6:lcd_activate 4 static
../src/lcd.c:123:6:ILI9341_Initial 8 static

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src/main.o src/main.d: ../src/main.c \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/LPC17xx.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cm3.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmInstr.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmFunc.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h \
../src/can.h ../src/callback.h ../src/accelo.h ../src/i2c.h \
../src/timer.h ../src/od.h ../src/lcd.h ../src/ssp.h
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/LPC17xx.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cm3.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmInstr.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmFunc.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h:
../src/can.h:
../src/callback.h:
../src/accelo.h:
../src/i2c.h:
../src/timer.h:
../src/od.h:
../src/lcd.h:
../src/ssp.h:

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/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cm3.h:1405:22:NVIC_SetPriority 16 static
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cm3.h:1532:26:SysTick_Config 16 static
../src/main.c:94:6:SysTick_Handler 4 static
../src/main.c:98:5:get_systick_counter 4 static
../src/main.c:113:6:affichage 16 static
../src/main.c:124:6:CANOpen_pdo1_send 16 static
../src/main.c:138:6:CANOpen_pdo1_receive 16 static
../src/main.c:146:6:CANOpen_pdo2_send 16 static
../src/main.c:159:6:CANOpen_pdo3_send 16 static
../src/main.c:172:6:CANOpen_pdo4_send 16 static
../src/main.c:187:6:get_data_from_i2c_and_ready_to_be_sent_to_master_then_send 8 static
../src/main.c:199:6:CAN_IRQHandler 16 static
../src/main.c:285:7:print_received_can_data 16 static
../src/main.c:292:6:callback_init 8 static
../src/main.c:301:6:CANOpen_NMT_send 16 static
../src/main.c:311:6:CANOpen_heartbeat_send 16 static
../src/main.c:320:5:slave_main 32 static
../src/main.c:370:6:master_main 40 static
../src/main.c:418:5:main 16 static

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src/od.o src/od.d: ../src/od.c ../src/od.h
../src/od.h:

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../src/od.c:135:12:get_OD_data 24 static
../src/od.c:146:6:set_OD_data 24 static

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../src/serie_5.c:23:6:CAN_IRQHandler 16 static
../src/serie_5.c:40:7:print_received_can_data 16 static
../src/serie_5.c:47:6:callback_init 8 static
../src/serie_5.c:53:5:main 16 static

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src/ssp.o src/ssp.d: ../src/ssp.c \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/LPC17xx.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cm3.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmInstr.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmFunc.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h \
../src/ssp.h
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/LPC17xx.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cm3.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmInstr.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmFunc.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h:
../src/ssp.h:

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../src/ssp.c:10:6:ssp_config 4 static
../src/ssp.c:32:6:ssp_send 16 static

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################################################################################
# Automatically-generated file. Do not edit!
################################################################################
# Add inputs and outputs from these tool invocations to the build variables
C_SRCS += \
../src/accelo.c \
../src/callback.c \
../src/can.c \
../src/cr_startup_lpc175x_6x.c \
../src/crp.c \
../src/i2c.c \
../src/lcd.c \
../src/main.c \
../src/od.c \
../src/ssp.c \
../src/timer.c \
../src/uart.c
OBJS += \
./src/accelo.o \
./src/callback.o \
./src/can.o \
./src/cr_startup_lpc175x_6x.o \
./src/crp.o \
./src/i2c.o \
./src/lcd.o \
./src/main.o \
./src/od.o \
./src/ssp.o \
./src/timer.o \
./src/uart.o
C_DEPS += \
./src/accelo.d \
./src/callback.d \
./src/can.d \
./src/cr_startup_lpc175x_6x.d \
./src/crp.d \
./src/i2c.d \
./src/lcd.d \
./src/main.d \
./src/od.d \
./src/ssp.d \
./src/timer.d \
./src/uart.d
# Each subdirectory must supply rules for building sources it contributes
src/%.o: ../src/%.c src/subdir.mk
@echo 'Building file: $<'
@echo 'Invoking: MCU C Compiler'
arm-none-eabi-gcc -DDEBUG -D__CODE_RED -DCORE_M3 -D__USE_CMSIS=CMSIS_CORE_LPC17xx -D__LPC17XX__ -D__REDLIB__ -DSDK_DEBUGCONSOLE=1 -I"/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc" -O0 -fno-common -g3 -Wall -c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -fmerge-constants -fmacro-prefix-map="$(<D)/"= -mcpu=cortex-m3 -mthumb -fstack-usage -specs=redlib.specs -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -MT"$(@:%.o=%.d)" -o "$@" "$<"
@echo 'Finished building: $<'
@echo ' '

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src/timer.o src/timer.d: ../src/timer.c ../src/timer.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/LPC17xx.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cm3.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmInstr.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmFunc.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h
../src/timer.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/LPC17xx.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cm3.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmInstr.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmFunc.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h:

BIN
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2
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/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cm3.h:1323:22:NVIC_EnableIRQ 16 static
../src/timer.c:31:6:timer_0_init 8 static

12
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src/uart.o src/uart.d: ../src/uart.c ../src/uart.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/LPC17xx.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cm3.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmInstr.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmFunc.h \
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h
../src/uart.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/LPC17xx.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cm3.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmInstr.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cmFunc.h:
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h:

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../src/uart.c:15:6:uart_init 16 static
../src/uart.c:50:6:uart_send 24 static
../src/uart.c:62:6:uart_receive 16 static

4
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@ -0,0 +1,4 @@
/home/yuyu/Documents/Documents/HEPIA/SPI/workspace/CMSIS_CORE_LPC17xx/inc/core_cm3.h:1323:22:NVIC_EnableIRQ 16 static
../src/uart2can2.c:21:6:can_config 8 static
../src/uart2can2.c:48:6:can_send 40 static
../src/uart2can2.c:85:6:can_receive 24 static

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199
Debug/uart2can-bin_bla_Debug.ld Normal file
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/*
* GENERATED FILE - DO NOT EDIT
* Copyright (c) 2008-2013 Code Red Technologies Ltd,
* Copyright 2015, 2018-2019 NXP
* (c) NXP Semiconductors 2013-2022
* Generated linker script file for LPC1769
* Created from linkscript.ldt by FMCreateLinkLibraries
* Using Freemarker v2.3.30
* MCUXpresso IDE v11.5.0 [Build 7232] [2022-01-11] on Jun 21, 2022, 4:03:31 PM
*/
INCLUDE "uart2can-bin_bla_Debug_library.ld"
INCLUDE "uart2can-bin_bla_Debug_memory.ld"
ENTRY(ResetISR)
SECTIONS
{
/* MAIN TEXT SECTION */
.text : ALIGN(4)
{
FILL(0xff)
__vectors_start__ = ABSOLUTE(.) ;
KEEP(*(.isr_vector))
/* Global Section Table */
. = ALIGN(4) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
LONG( ADDR(.data));
LONG( SIZEOF(.data));
LONG(LOADADDR(.data_RAM2));
LONG( ADDR(.data_RAM2));
LONG( SIZEOF(.data_RAM2));
__data_section_table_end = .;
__bss_section_table = .;
LONG( ADDR(.bss));
LONG( SIZEOF(.bss));
LONG( ADDR(.bss_RAM2));
LONG( SIZEOF(.bss_RAM2));
__bss_section_table_end = .;
__section_table_end = . ;
/* End of Global Section Table */
*(.after_vectors*)
/* Code Read Protection data */
. = 0x000002FC ;
PROVIDE(__CRP_WORD_START__ = .) ;
KEEP(*(.crp))
PROVIDE(__CRP_WORD_END__ = .) ;
ASSERT(!(__CRP_WORD_START__ == __CRP_WORD_END__), "Linker CRP Enabled, but no CRP_WORD provided within application");
/* End of Code Read Protection */
*(.text*)
*(.rodata .rodata.* .constdata .constdata.*)
. = ALIGN(4);
} > MFlash512
/*
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
.ARM.extab : ALIGN(4)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash512
.ARM.exidx : ALIGN(4)
{
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
} > MFlash512
_etext = .;
/* DATA section for RamAHB32 */
.data_RAM2 : ALIGN(4)
{
FILL(0xff)
PROVIDE(__start_data_RAM2 = .) ;
PROVIDE(__start_data_RamAHB32 = .) ;
*(.ramfunc.$RAM2)
*(.ramfunc.$RamAHB32)
*(.data.$RAM2)
*(.data.$RamAHB32)
*(.data.$RAM2.*)
*(.data.$RamAHB32.*)
. = ALIGN(4) ;
PROVIDE(__end_data_RAM2 = .) ;
PROVIDE(__end_data_RamAHB32 = .) ;
} > RamAHB32 AT>MFlash512
/* MAIN DATA SECTION */
.uninit_RESERVED (NOLOAD) : ALIGN(4)
{
_start_uninit_RESERVED = .;
KEEP(*(.bss.$RESERVED*))
. = ALIGN(4) ;
_end_uninit_RESERVED = .;
} > RamLoc32 AT> RamLoc32
/* Main DATA section (RamLoc32) */
.data : ALIGN(4)
{
FILL(0xff)
_data = . ;
PROVIDE(__start_data_RAM = .) ;
PROVIDE(__start_data_RamLoc32 = .) ;
*(vtable)
*(.ramfunc*)
KEEP(*(CodeQuickAccess))
KEEP(*(DataQuickAccess))
*(RamFunction)
*(.data*)
. = ALIGN(4) ;
_edata = . ;
PROVIDE(__end_data_RAM = .) ;
PROVIDE(__end_data_RamLoc32 = .) ;
} > RamLoc32 AT>MFlash512
/* BSS section for RamAHB32 */
.bss_RAM2 : ALIGN(4)
{
PROVIDE(__start_bss_RAM2 = .) ;
PROVIDE(__start_bss_RamAHB32 = .) ;
*(.bss.$RAM2)
*(.bss.$RamAHB32)
*(.bss.$RAM2.*)
*(.bss.$RamAHB32.*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM2 = .) ;
PROVIDE(__end_bss_RamAHB32 = .) ;
} > RamAHB32 AT> RamAHB32
/* MAIN BSS SECTION */
.bss : ALIGN(4)
{
_bss = .;
PROVIDE(__start_bss_RAM = .) ;
PROVIDE(__start_bss_RamLoc32 = .) ;
*(.bss*)
*(COMMON)
. = ALIGN(4) ;
_ebss = .;
PROVIDE(__end_bss_RAM = .) ;
PROVIDE(__end_bss_RamLoc32 = .) ;
PROVIDE(end = .);
} > RamLoc32 AT> RamLoc32
/* NOINIT section for RamAHB32 */
.noinit_RAM2 (NOLOAD) : ALIGN(4)
{
PROVIDE(__start_noinit_RAM2 = .) ;
PROVIDE(__start_noinit_RamAHB32 = .) ;
*(.noinit.$RAM2)
*(.noinit.$RamAHB32)
*(.noinit.$RAM2.*)
*(.noinit.$RamAHB32.*)
. = ALIGN(4) ;
PROVIDE(__end_noinit_RAM2 = .) ;
PROVIDE(__end_noinit_RamAHB32 = .) ;
} > RamAHB32 AT> RamAHB32
/* DEFAULT NOINIT SECTION */
.noinit (NOLOAD): ALIGN(4)
{
_noinit = .;
PROVIDE(__start_noinit_RAM = .) ;
PROVIDE(__start_noinit_RamLoc32 = .) ;
*(.noinit*)
. = ALIGN(4) ;
_end_noinit = .;
PROVIDE(__end_noinit_RAM = .) ;
PROVIDE(__end_noinit_RamLoc32 = .) ;
} > RamLoc32 AT> RamLoc32
PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
/* ## Create checksum value (used in startup) ## */
PROVIDE(__valid_user_code_checksum = 0 -
(_vStackTop
+ (ResetISR + 1)
+ (NMI_Handler + 1)
+ (HardFault_Handler + 1)
+ (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
+ (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
+ (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
) );
/* Provide basic symbols giving location and size of main text
* block, including initial values of RW data sections. Note that
* these will need extending to give a complete picture with
* complex images (e.g multiple Flash banks).
*/
_image_start = LOADADDR(.text);
_image_end = LOADADDR(.data) + SIZEOF(.data);
_image_size = _image_end - _image_start;
}

17
Debug/uart2can-bin_bla_Debug_library.ld Normal file
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@ -0,0 +1,17 @@
/*
* GENERATED FILE - DO NOT EDIT
* Copyright (c) 2008-2013 Code Red Technologies Ltd,
* Copyright 2015, 2018-2019 NXP
* (c) NXP Semiconductors 2013-2022
* Generated linker script file for LPC1769
* Created from library.ldt by FMCreateLinkLibraries
* Using Freemarker v2.3.30
* MCUXpresso IDE v11.5.0 [Build 7232] [2022-01-11] on Jun 21, 2022, 4:03:31 PM
*/
GROUP (
"libcr_semihost.a"
"libcr_c.a"
"libcr_eabihelpers.a"
"libgcc.a"
)

32
Debug/uart2can-bin_bla_Debug_memory.ld Normal file
View File

@ -0,0 +1,32 @@
/*
* GENERATED FILE - DO NOT EDIT
* Copyright (c) 2008-2013 Code Red Technologies Ltd,
* Copyright 2015, 2018-2019 NXP
* (c) NXP Semiconductors 2013-2022
* Generated linker script file for LPC1769
* Created from memory.ldt by FMCreateLinkMemory
* Using Freemarker v2.3.30
* MCUXpresso IDE v11.5.0 [Build 7232] [2022-01-11] on Jun 21, 2022, 4:03:31 PM
*/
MEMORY
{
/* Define each memory region */
MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */
}
/* Define a symbol for the top of each memory region */
__base_MFlash512 = 0x0 ; /* MFlash512 */
__base_Flash = 0x0 ; /* Flash */
__top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */
__top_Flash = 0x0 + 0x80000 ; /* 512K bytes */
__base_RamLoc32 = 0x10000000 ; /* RamLoc32 */
__base_RAM = 0x10000000 ; /* RAM */
__top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
__top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
__base_RamAHB32 = 0x2007c000 ; /* RamAHB32 */
__base_RAM2 = 0x2007c000 ; /* RAM2 */
__top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */
__top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */

199
Debug/uart2can_Debug.ld Normal file
View File

@ -0,0 +1,199 @@
/*
* GENERATED FILE - DO NOT EDIT
* Copyright (c) 2008-2013 Code Red Technologies Ltd,
* Copyright 2015, 2018-2019 NXP
* (c) NXP Semiconductors 2013-2022
* Generated linker script file for LPC1769
* Created from linkscript.ldt by FMCreateLinkLibraries
* Using Freemarker v2.3.30
* MCUXpresso IDE v11.5.0 [Build 7232] [2022-01-11] on Apr 7, 2022, 4:16:52 PM
*/
INCLUDE "uart2can_Debug_library.ld"
INCLUDE "uart2can_Debug_memory.ld"
ENTRY(ResetISR)
SECTIONS
{
/* MAIN TEXT SECTION */
.text : ALIGN(4)
{
FILL(0xff)
__vectors_start__ = ABSOLUTE(.) ;
KEEP(*(.isr_vector))
/* Global Section Table */
. = ALIGN(4) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
LONG( ADDR(.data));
LONG( SIZEOF(.data));
LONG(LOADADDR(.data_RAM2));
LONG( ADDR(.data_RAM2));
LONG( SIZEOF(.data_RAM2));
__data_section_table_end = .;
__bss_section_table = .;
LONG( ADDR(.bss));
LONG( SIZEOF(.bss));
LONG( ADDR(.bss_RAM2));
LONG( SIZEOF(.bss_RAM2));
__bss_section_table_end = .;
__section_table_end = . ;
/* End of Global Section Table */
*(.after_vectors*)
/* Code Read Protection data */
. = 0x000002FC ;
PROVIDE(__CRP_WORD_START__ = .) ;
KEEP(*(.crp))
PROVIDE(__CRP_WORD_END__ = .) ;
ASSERT(!(__CRP_WORD_START__ == __CRP_WORD_END__), "Linker CRP Enabled, but no CRP_WORD provided within application");
/* End of Code Read Protection */
*(.text*)
*(.rodata .rodata.* .constdata .constdata.*)
. = ALIGN(4);
} > MFlash512
/*
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
.ARM.extab : ALIGN(4)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash512
.ARM.exidx : ALIGN(4)
{
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
} > MFlash512
_etext = .;
/* DATA section for RamAHB32 */
.data_RAM2 : ALIGN(4)
{
FILL(0xff)
PROVIDE(__start_data_RAM2 = .) ;
PROVIDE(__start_data_RamAHB32 = .) ;
*(.ramfunc.$RAM2)
*(.ramfunc.$RamAHB32)
*(.data.$RAM2)
*(.data.$RamAHB32)
*(.data.$RAM2.*)
*(.data.$RamAHB32.*)
. = ALIGN(4) ;
PROVIDE(__end_data_RAM2 = .) ;
PROVIDE(__end_data_RamAHB32 = .) ;
} > RamAHB32 AT>MFlash512
/* MAIN DATA SECTION */
.uninit_RESERVED (NOLOAD) : ALIGN(4)
{
_start_uninit_RESERVED = .;
KEEP(*(.bss.$RESERVED*))
. = ALIGN(4) ;
_end_uninit_RESERVED = .;
} > RamLoc32 AT> RamLoc32
/* Main DATA section (RamLoc32) */
.data : ALIGN(4)
{
FILL(0xff)
_data = . ;
PROVIDE(__start_data_RAM = .) ;
PROVIDE(__start_data_RamLoc32 = .) ;
*(vtable)
*(.ramfunc*)
KEEP(*(CodeQuickAccess))
KEEP(*(DataQuickAccess))
*(RamFunction)
*(.data*)
. = ALIGN(4) ;
_edata = . ;
PROVIDE(__end_data_RAM = .) ;
PROVIDE(__end_data_RamLoc32 = .) ;
} > RamLoc32 AT>MFlash512
/* BSS section for RamAHB32 */
.bss_RAM2 : ALIGN(4)
{
PROVIDE(__start_bss_RAM2 = .) ;
PROVIDE(__start_bss_RamAHB32 = .) ;
*(.bss.$RAM2)
*(.bss.$RamAHB32)
*(.bss.$RAM2.*)
*(.bss.$RamAHB32.*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM2 = .) ;
PROVIDE(__end_bss_RamAHB32 = .) ;
} > RamAHB32 AT> RamAHB32
/* MAIN BSS SECTION */
.bss : ALIGN(4)
{
_bss = .;
PROVIDE(__start_bss_RAM = .) ;
PROVIDE(__start_bss_RamLoc32 = .) ;
*(.bss*)
*(COMMON)
. = ALIGN(4) ;
_ebss = .;
PROVIDE(__end_bss_RAM = .) ;
PROVIDE(__end_bss_RamLoc32 = .) ;
PROVIDE(end = .);
} > RamLoc32 AT> RamLoc32
/* NOINIT section for RamAHB32 */
.noinit_RAM2 (NOLOAD) : ALIGN(4)
{
PROVIDE(__start_noinit_RAM2 = .) ;
PROVIDE(__start_noinit_RamAHB32 = .) ;
*(.noinit.$RAM2)
*(.noinit.$RamAHB32)
*(.noinit.$RAM2.*)
*(.noinit.$RamAHB32.*)
. = ALIGN(4) ;
PROVIDE(__end_noinit_RAM2 = .) ;
PROVIDE(__end_noinit_RamAHB32 = .) ;
} > RamAHB32 AT> RamAHB32
/* DEFAULT NOINIT SECTION */
.noinit (NOLOAD): ALIGN(4)
{
_noinit = .;
PROVIDE(__start_noinit_RAM = .) ;
PROVIDE(__start_noinit_RamLoc32 = .) ;
*(.noinit*)
. = ALIGN(4) ;
_end_noinit = .;
PROVIDE(__end_noinit_RAM = .) ;
PROVIDE(__end_noinit_RamLoc32 = .) ;
} > RamLoc32 AT> RamLoc32
PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
/* ## Create checksum value (used in startup) ## */
PROVIDE(__valid_user_code_checksum = 0 -
(_vStackTop
+ (ResetISR + 1)
+ (NMI_Handler + 1)
+ (HardFault_Handler + 1)
+ (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
+ (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
+ (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
) );
/* Provide basic symbols giving location and size of main text
* block, including initial values of RW data sections. Note that
* these will need extending to give a complete picture with
* complex images (e.g multiple Flash banks).
*/
_image_start = LOADADDR(.text);
_image_end = LOADADDR(.data) + SIZEOF(.data);
_image_size = _image_end - _image_start;
}

17
Debug/uart2can_Debug_library.ld Normal file
View File

@ -0,0 +1,17 @@
/*
* GENERATED FILE - DO NOT EDIT
* Copyright (c) 2008-2013 Code Red Technologies Ltd,
* Copyright 2015, 2018-2019 NXP
* (c) NXP Semiconductors 2013-2022
* Generated linker script file for LPC1769
* Created from library.ldt by FMCreateLinkLibraries
* Using Freemarker v2.3.30
* MCUXpresso IDE v11.5.0 [Build 7232] [2022-01-11] on Apr 7, 2022, 4:16:52 PM
*/
GROUP (
"libcr_nohost.a"
"libcr_c.a"
"libcr_eabihelpers.a"
"libgcc.a"
)

32
Debug/uart2can_Debug_memory.ld Normal file
View File

@ -0,0 +1,32 @@
/*
* GENERATED FILE - DO NOT EDIT
* Copyright (c) 2008-2013 Code Red Technologies Ltd,
* Copyright 2015, 2018-2019 NXP
* (c) NXP Semiconductors 2013-2022
* Generated linker script file for LPC1769
* Created from memory.ldt by FMCreateLinkMemory
* Using Freemarker v2.3.30
* MCUXpresso IDE v11.5.0 [Build 7232] [2022-01-11] on Apr 7, 2022, 4:16:52 PM
*/
MEMORY
{
/* Define each memory region */
MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */
}
/* Define a symbol for the top of each memory region */
__base_MFlash512 = 0x0 ; /* MFlash512 */
__base_Flash = 0x0 ; /* Flash */
__top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */
__top_Flash = 0x0 + 0x80000 ; /* 512K bytes */
__base_RamLoc32 = 0x10000000 ; /* RamLoc32 */
__base_RAM = 0x10000000 ; /* RAM */
__top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
__top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
__base_RamAHB32 = 0x2007c000 ; /* RamAHB32 */
__base_RAM2 = 0x2007c000 ; /* RAM2 */
__top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */
__top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */