example_code upload

example_code/i2c/dma_b2b_transfer/master/board.c

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+/*
+ * Copyright 2017-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "board.h"
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+#include "fsl_i2c.h"
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+    /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
+    CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+
+    RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST);
+
+    uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+
+    DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz)
+{
+    i2c_master_config_t i2cConfig = {0};
+
+    I2C_MasterGetDefaultConfig(&i2cConfig);
+    I2C_MasterInit(base, &i2cConfig, clkSrc_Hz);
+}
+
+status_t BOARD_I2C_Send(I2C_Type *base,
+                        uint8_t deviceAddress,
+                        uint32_t subAddress,
+                        uint8_t subaddressSize,
+                        uint8_t *txBuff,
+                        uint8_t txBuffSize)
+{
+    i2c_master_transfer_t masterXfer;
+
+    /* Prepare transfer structure. */
+    masterXfer.slaveAddress   = deviceAddress;
+    masterXfer.direction      = kI2C_Write;
+    masterXfer.subaddress     = subAddress;
+    masterXfer.subaddressSize = subaddressSize;
+    masterXfer.data           = txBuff;
+    masterXfer.dataSize       = txBuffSize;
+    masterXfer.flags          = kI2C_TransferDefaultFlag;
+
+    return I2C_MasterTransferBlocking(base, &masterXfer);
+}
+
+status_t BOARD_I2C_Receive(I2C_Type *base,
+                           uint8_t deviceAddress,
+                           uint32_t subAddress,
+                           uint8_t subaddressSize,
+                           uint8_t *rxBuff,
+                           uint8_t rxBuffSize)
+{
+    i2c_master_transfer_t masterXfer;
+
+    /* Prepare transfer structure. */
+    masterXfer.slaveAddress   = deviceAddress;
+    masterXfer.subaddress     = subAddress;
+    masterXfer.subaddressSize = subaddressSize;
+    masterXfer.data           = rxBuff;
+    masterXfer.dataSize       = rxBuffSize;
+    masterXfer.direction      = kI2C_Read;
+    masterXfer.flags          = kI2C_TransferDefaultFlag;
+
+    return I2C_MasterTransferBlocking(base, &masterXfer);
+}
+
+void BOARD_Accel_I2C_Init(void)
+{
+    BOARD_I2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
+{
+    uint8_t data = (uint8_t)txBuff;
+
+    return BOARD_I2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
+}
+
+status_t BOARD_Accel_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+    return BOARD_I2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
+}
+
+void BOARD_Codec_I2C_Init(void)
+{
+    BOARD_I2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Codec_I2C_Send(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
+{
+    return BOARD_I2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
+                          txBuffSize);
+}
+
+status_t BOARD_Codec_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+    return BOARD_I2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
+}
+#endif /* SDK_I2C_BASED_COMPONENT_USED */

example_code/i2c/dma_b2b_transfer/master/board.h

@@ -0,0 +1,230 @@
+/*
+ * Copyright 2017-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "clock_config.h"
+#include "fsl_common.h"
+#include "fsl_reset.h"
+#include "fsl_gpio.h"
+#include "fsl_iocon.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "LPCXpresso55S16"
+
+/*! @brief The UART to use for debug messages. */
+/* TODO: rename UART to USART */
+#define BOARD_DEBUG_UART_TYPE       kSerialPort_Uart
+#define BOARD_DEBUG_UART_BASEADDR   (uint32_t) USART0
+#define BOARD_DEBUG_UART_INSTANCE   0U
+#define BOARD_DEBUG_UART_CLK_FREQ   12000000U
+#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM0
+#define BOARD_DEBUG_UART_RST        kFC0_RST_SHIFT_RSTn
+#define BOARD_DEBUG_UART_CLKSRC     kCLOCK_Flexcomm0
+#define BOARD_UART_IRQ_HANDLER      FLEXCOMM0_IRQHandler
+#define BOARD_UART_IRQ              FLEXCOMM0_IRQn
+
+#define BOARD_ACCEL_I2C_BASEADDR   I2C4
+#define BOARD_ACCEL_I2C_CLOCK_FREQ 12000000
+
+#ifndef BOARD_DEBUG_UART_BAUDRATE
+#define BOARD_DEBUG_UART_BAUDRATE 115200U
+#endif /* BOARD_DEBUG_UART_BAUDRATE */
+
+#define BOARD_CODEC_I2C_BASEADDR   I2C4
+#define BOARD_CODEC_I2C_CLOCK_FREQ 12000000
+#define BOARD_CODEC_I2C_INSTANCE   4
+#ifndef BOARD_LED_RED_GPIO
+#define BOARD_LED_RED_GPIO GPIO
+#endif
+#define BOARD_LED_RED_GPIO_PORT 1U
+#ifndef BOARD_LED_RED_GPIO_PIN
+#define BOARD_LED_RED_GPIO_PIN 4U
+#endif
+
+#ifndef BOARD_LED_BLUE_GPIO
+#define BOARD_LED_BLUE_GPIO GPIO
+#endif
+#define BOARD_LED_BLUE_GPIO_PORT 1U
+#ifndef BOARD_LED_BLUE_GPIO_PIN
+#define BOARD_LED_BLUE_GPIO_PIN 6U
+#endif
+
+#ifndef BOARD_LED_GREEN_GPIO
+#define BOARD_LED_GREEN_GPIO GPIO
+#endif
+#define BOARD_LED_GREEN_GPIO_PORT 1U
+#ifndef BOARD_LED_GREEN_GPIO_PIN
+#define BOARD_LED_GREEN_GPIO_PIN 7U
+#endif
+
+#ifndef BOARD_SW1_GPIO
+#define BOARD_SW1_GPIO GPIO
+#endif
+#define BOARD_SW1_GPIO_PORT 1U
+#ifndef BOARD_SW1_GPIO_PIN
+#define BOARD_SW1_GPIO_PIN 18U
+#endif
+#define BOARD_SW1_NAME        "SW1"
+#define BOARD_SW1_IRQ         PIN_INT1_IRQn
+#define BOARD_SW1_IRQ_HANDLER PIN_INT1_IRQHandler
+
+#ifndef BOARD_SW3_GPIO
+#define BOARD_SW3_GPIO GPIO
+#endif
+#define BOARD_SW3_GPIO_PORT 1U
+#ifndef BOARD_SW3_GPIO_PIN
+#define BOARD_SW3_GPIO_PIN 9U
+#endif
+#define BOARD_SW3_NAME              "SW3"
+#define BOARD_SW3_IRQ               PIN_INT1_IRQn
+#define BOARD_SW3_IRQ_HANDLER       PIN_INT1_IRQHandler
+#define BOARD_SW3_GPIO_PININT_INDEX 1
+
+#ifndef BOARD_SW4_GPIO
+#define BOARD_SW4_GPIO GPIO
+#endif
+#define BOARD_SW4_GPIO_PORT 0U
+#ifndef BOARD_SW4_GPIO_PIN
+#define BOARD_SW4_GPIO_PIN 5U
+#endif
+#define BOARD_SW4_NAME              "SW4"
+#define BOARD_SW4_IRQ               PIN_INT0_IRQn
+#define BOARD_SW4_IRQ_HANDLER       PIN_INT0_IRQHandler
+#define BOARD_SW4_GPIO_PININT_INDEX 1
+
+/* USB PHY condfiguration */
+#define BOARD_USB_PHY_D_CAL     (0x05U)
+#define BOARD_USB_PHY_TXCAL45DP (0x0AU)
+#define BOARD_USB_PHY_TXCAL45DM (0x0AU)
+
+#define BOARD_SDIF_BASEADDR       SDIF
+#define BOARD_SDIF_CLKSRC         kCLOCK_SDio
+#define BOARD_SDIF_CLK_FREQ       CLOCK_GetSdioClkFreq()
+#define BOARD_SDIF_CLK_ATTACH     kMAIN_CLK_to_SDIO_CLK
+#define BOARD_SDIF_IRQ            SDIO_IRQn
+#define BOARD_MMC_VCC_SUPPLY      kMMC_VoltageWindows270to360
+#define BOARD_SD_CARD_DETECT_PIN  17
+#define BOARD_SD_CARD_DETECT_PORT 0
+#define BOARD_SD_CARD_DETECT_GPIO GPIO
+#define BOARD_SD_DETECT_TYPE      kSDMMCHOST_DetectCardByHostCD
+
+#define BOARD_SDIF_CD_GPIO_INIT()                                                                    \
+    {                                                                                                \
+        CLOCK_EnableClock(kCLOCK_Gpio2);                                                             \
+        GPIO_PinInit(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN, \
+                     &(gpio_pin_config_t){kGPIO_DigitalInput, 0U});                                  \
+    }
+#define BOARD_SDIF_CD_STATUS() \
+    GPIO_PinRead(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN)
+
+/* Board led color mapping */
+#define LOGIC_LED_ON  1U
+#define LOGIC_LED_OFF 0U
+
+#define BOARD_SDIF_CLK_ATTACH kMAIN_CLK_to_SDIO_CLK
+
+#define LED_RED_INIT(output)                                                                          \
+    {                                                                                                 \
+        IOCON_PinMuxSet(IOCON, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, IOCON_DIGITAL_EN);    \
+        GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN,             \
+                     &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \
+    }
+#define LED_RED_OFF()                                           \
+    GPIO_PortClear(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+                   1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED1 */
+#define LED_RED_ON()                                                                        \
+    GPIO_PortSet(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT,                               \
+                 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED1 \ \ \ \ \ \ \ \ \ \ \
+                                                */
+#define LED_RED_TOGGLE()                                         \
+    GPIO_PortToggle(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+                    1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED1 */
+
+#define LED_BLUE_INIT(output)                                                                         \
+    {                                                                                                 \
+        IOCON_PinMuxSet(IOCON, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, IOCON_DIGITAL_EN);  \
+        GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN,          \
+                     &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \
+    }
+#define LED_BLUE_OFF()                                            \
+    GPIO_PortClear(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                   1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED1 */
+#define LED_BLUE_ON()                                           \
+    GPIO_PortSet(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED1 */
+#define LED_BLUE_TOGGLE()                                          \
+    GPIO_PortToggle(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                    1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED1 */
+
+#define LED_GREEN_INIT(output)                                                              \
+    GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, BOARD_LED_GREEN_GPIO_PIN, \
+                 &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED1 */
+#define LED_GREEN_OFF()                                             \
+    GPIO_PortClear(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                   1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED1 */
+#define LED_GREEN_ON()                                            \
+    GPIO_PortSet(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED1 */
+#define LED_GREEN_TOGGLE()                                           \
+    GPIO_PortToggle(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                    1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED1 */
+
+/* Display. */
+#define BOARD_LCD_DC_GPIO      GPIO
+#define BOARD_LCD_DC_GPIO_PORT 1U
+#define BOARD_LCD_DC_GPIO_PIN  5U
+
+/* Serial MWM WIFI */
+#define BOARD_SERIAL_MWM_PORT_CLK_FREQ CLOCK_GetFlexCommClkFreq(2)
+#define BOARD_SERIAL_MWM_PORT          USART2
+#define BOARD_SERIAL_MWM_PORT_IRQn     FLEXCOMM2_IRQn
+#define BOARD_SERIAL_MWM_RST_WRITE(output)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz);
+status_t BOARD_I2C_Send(I2C_Type *base,
+                        uint8_t deviceAddress,
+                        uint32_t subAddress,
+                        uint8_t subaddressSize,
+                        uint8_t *txBuff,
+                        uint8_t txBuffSize);
+status_t BOARD_I2C_Receive(I2C_Type *base,
+                           uint8_t deviceAddress,
+                           uint32_t subAddress,
+                           uint8_t subaddressSize,
+                           uint8_t *rxBuff,
+                           uint8_t rxBuffSize);
+void BOARD_Accel_I2C_Init(void);
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
+status_t BOARD_Accel_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+void BOARD_Codec_I2C_Init(void);
+status_t BOARD_Codec_I2C_Send(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
+status_t BOARD_Codec_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */

example_code/i2c/dma_b2b_transfer/master/clock_config.c

@@ -0,0 +1,380 @@
+/*
+ * Copyright 2017-2018 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to set up clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up wait states of the flash.
+ *
+ * 3. Set up all dividers.
+ *
+ * 4. Set up all selectors to provide selected clocks.
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v7.0
+processor: LPC55S16
+package_id: LPC55S16JBD100
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+board: LPCXpresso55S16
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockPLL150M();
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 12 MHz}
+settings:
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    POWER_SetVoltageForFreq(12000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(12000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO12M */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF96M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF96M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    POWER_SetVoltageForFreq(96000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(96000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL100M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 100 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
+- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
+- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL100M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable High speed Crystal oscillator output to system  */
+
+    POWER_SetVoltageForFreq(100000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(100000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U),
+        .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
+        .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
+        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+        .pllRate = 100000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL150M
+called_from_default_init: true
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 150 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true}
+- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true}
+- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true}
+sources:
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL150M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable High speed Crystal oscillator output to system  */
+
+    POWER_SetVoltageForFreq(150000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(150000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
+        .pllndec = SYSCON_PLL0NDEC_NDIV(8U),
+        .pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
+        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+        .pllRate = 150000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockPLL1_150M ********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL1_150M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 150 MHz}
+settings:
+- {id: PLL1_Mode, value: Normal}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS}
+- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL1M_MULT.scale, value: '150', locked: true}
+- {id: SYSCON.PLL1N_DIV.scale, value: '8', locked: true}
+- {id: SYSCON.PLL1_PDEC.scale, value: '2', locked: true}
+sources:
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL1_150M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable High speed Crystal oscillator output to system  */
+
+    POWER_SetVoltageForFreq(150000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(150000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL1 */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL1);                    /*!< Switch PLL1CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL1);                  /* Ensure PLL is on  */
+    const pll_setup_t pll1Setup = {
+        .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(53U) | SYSCON_PLL1CTRL_SELP(31U),
+        .pllndec = SYSCON_PLL1NDEC_NDIV(8U),
+        .pllpdec = SYSCON_PLL1PDEC_PDIV(1U),
+        .pllmdec = SYSCON_PLL1MDEC_MDIV(150U),
+        .pllRate = 150000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL1Freq(&pll1Setup);                        /*!< Configure PLL1 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL1_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL1 */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK;
+#endif
+}
+

example_code/i2c/dma_b2b_transfer/master/clock_config.h

@@ -0,0 +1,173 @@
+/*
+ * Copyright 2017-2018 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         16000000U  /*!< Board xtal frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK         96000000U  /*!< Core clock frequency: 96000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF96M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL100M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         150000000U  /*!< Core clock frequency: 150000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockPLL1_150M ********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK       150000000U  /*!< Core clock frequency: 150000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL1_150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+

example_code/i2c/dma_b2b_transfer/master/i2c_dma_b2b_transfer_master.c

@@ -0,0 +1,192 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*  SDK Included Files */
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_debug_console.h"
+#include "fsl_i2c.h"
+#include "fsl_i2c_dma.h"
+
+#include "fsl_power.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define EXAMPLE_I2C_MASTER_BASE    (I2C4_BASE)
+#define I2C_MASTER_CLOCK_FREQUENCY (12000000)
+
+#define EXAMPLE_DMA                DMA0
+#define EXAMPLE_I2C_MASTER_CHANNEL 13
+
+#define EXAMPLE_I2C_MASTER ((I2C_Type *)EXAMPLE_I2C_MASTER_BASE)
+
+#define I2C_MASTER_SLAVE_ADDR_7BIT (0x7EU)
+#define I2C_BAUDRATE               (100000) /* 100K */
+#define I2C_DATA_LENGTH            (33)     /* MAX is 256 */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+uint8_t g_master_txBuff[I2C_DATA_LENGTH];
+uint8_t g_master_rxBuff[I2C_DATA_LENGTH];
+
+i2c_master_dma_handle_t g_m_dma_handle;
+dma_handle_t dmaHandle;
+volatile bool g_MasterCompletionFlag = false;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static void i2c_master_dma_callback(I2C_Type *base, i2c_master_dma_handle_t *handle, status_t status, void *userData)
+{
+    /* Signal transfer success when received success status. */
+    if (status == kStatus_Success)
+    {
+        g_MasterCompletionFlag = true;
+    }
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+    i2c_master_config_t masterConfig;
+    i2c_master_transfer_t masterXfer;
+
+    /* set BOD VBAT level to 1.65V */
+    POWER_SetBodVbatLevel(kPOWER_BodVbatLevel1650mv, kPOWER_BodHystLevel50mv, false);
+    /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
+    CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+
+    /* attach 12 MHz clock to FLEXCOMM4 (I2C master) */
+    CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
+
+    /* reset FLEXCOMM for I2C */
+    RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn);
+
+    BOARD_InitBootPins();
+    BOARD_InitBootClocks();
+    BOARD_InitDebugConsole();
+
+    DMA_Init(EXAMPLE_DMA);
+
+    PRINTF("\r\nI2C board2board DMA example -- Master transfer.\r\n");
+
+    /* Set up i2c master to send data to slave*/
+    /* First data in txBuff is data length of the transmiting data. */
+    g_master_txBuff[0] = I2C_DATA_LENGTH - 1U;
+    for (uint32_t i = 1U; i < I2C_DATA_LENGTH; i++)
+    {
+        g_master_txBuff[i] = i - 1;
+    }
+
+    PRINTF("Master will send data :");
+    for (uint32_t i = 0U; i < I2C_DATA_LENGTH - 1U; i++)
+    {
+        if (i % 8 == 0)
+        {
+            PRINTF("\r\n");
+        }
+        PRINTF("0x%2x  ", g_master_txBuff[i + 1]);
+    }
+    PRINTF("\r\n\r\n");
+
+    /*
+     * masterConfig.baudRate_Bps = 100000U;
+     * masterConfig.enableStopHold = false;
+     * masterConfig.glitchFilterWidth = 0U;
+     * masterConfig.enableMaster = true;
+     */
+    I2C_MasterGetDefaultConfig(&masterConfig);
+
+    /* Change the default baudrate configuration */
+    masterConfig.baudRate_Bps = I2C_BAUDRATE;
+
+    /* Initialize the I2C master peripheral */
+    I2C_MasterInit(EXAMPLE_I2C_MASTER, &masterConfig, I2C_MASTER_CLOCK_FREQUENCY);
+
+    memset(&g_m_dma_handle, 0, sizeof(g_m_dma_handle));
+    memset(&masterXfer, 0, sizeof(masterXfer));
+
+    /* subAddress = 0x01, data = g_master_txBuff - write to slave.
+      start + slaveaddress(w) + subAddress + length of data buffer + data buffer + stop*/
+    uint8_t deviceAddress     = 0x01U;
+    masterXfer.slaveAddress   = I2C_MASTER_SLAVE_ADDR_7BIT;
+    masterXfer.direction      = kI2C_Write;
+    masterXfer.subaddress     = (uint32_t)deviceAddress;
+    masterXfer.subaddressSize = 1;
+    masterXfer.data           = g_master_txBuff;
+    masterXfer.dataSize       = I2C_DATA_LENGTH;
+    masterXfer.flags          = kI2C_TransferDefaultFlag;
+
+    DMA_EnableChannel(EXAMPLE_DMA, EXAMPLE_I2C_MASTER_CHANNEL);
+    DMA_CreateHandle(&dmaHandle, EXAMPLE_DMA, EXAMPLE_I2C_MASTER_CHANNEL);
+
+    I2C_MasterTransferCreateHandleDMA(EXAMPLE_I2C_MASTER, &g_m_dma_handle, i2c_master_dma_callback, NULL, &dmaHandle);
+    I2C_MasterTransferDMA(EXAMPLE_I2C_MASTER, &g_m_dma_handle, &masterXfer);
+
+    /*  wait for transfer completed. */
+    while (!g_MasterCompletionFlag)
+    {
+    }
+    g_MasterCompletionFlag = false;
+
+    PRINTF("Receive sent data from slave :");
+
+    /* subAddress = 0x01, data = g_master_rxBuff - read from slave.
+      start + slaveaddress(w) + subAddress + repeated start + slaveaddress(r) + rx data buffer + stop */
+    masterXfer.slaveAddress   = I2C_MASTER_SLAVE_ADDR_7BIT;
+    masterXfer.direction      = kI2C_Read;
+    masterXfer.subaddress     = (uint32_t)deviceAddress;
+    masterXfer.subaddressSize = 1;
+    masterXfer.data           = g_master_rxBuff;
+    masterXfer.dataSize       = I2C_DATA_LENGTH - 1;
+    masterXfer.flags          = kI2C_TransferDefaultFlag;
+
+    I2C_MasterTransferDMA(EXAMPLE_I2C_MASTER, &g_m_dma_handle, &masterXfer);
+
+    /*  Reset master completion flag to false. */
+    g_MasterCompletionFlag = false;
+
+    /*  Wait for transfer completed. */
+    while (!g_MasterCompletionFlag)
+    {
+    }
+    g_MasterCompletionFlag = false;
+
+    for (uint32_t i = 0U; i < I2C_DATA_LENGTH - 1; i++)
+    {
+        if (i % 8 == 0)
+        {
+            PRINTF("\r\n");
+        }
+        PRINTF("0x%2x  ", g_master_rxBuff[i]);
+    }
+    PRINTF("\r\n\r\n");
+
+    /* Transfer completed. Check the data.*/
+    for (uint32_t i = 0U; i < I2C_DATA_LENGTH - 1; i++)
+    {
+        if (g_master_rxBuff[i] != g_master_txBuff[i + 1])
+        {
+            PRINTF("\r\nError occurred in the transfer ! \r\n");
+            break;
+        }
+    }
+
+    PRINTF("\r\nEnd of I2C example .\r\n");
+    while (1)
+    {
+    }
+}

example_code/i2c/dma_b2b_transfer/master/i2c_dma_b2b_transfer_master_v3_9.xml

@@ -0,0 +1,126 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<ksdk:examples xmlns:ksdk="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd manifest.xsd">
+  <externalDefinitions>
+    <definition extID="utility.debug_console_lite.LPC55S16"/>
+    <definition extID="platform.utilities.assert_lite.LPC55S16"/>
+    <definition extID="platform.drivers.lpc_dma.LPC55S16"/>
+    <definition extID="platform.drivers.flexcomm_i2c.LPC55S16"/>
+    <definition extID="platform.drivers.flexcomm_i2c_dma.LPC55S16"/>
+    <definition extID="platform.drivers.common.LPC55S16"/>
+    <definition extID="platform.drivers.power.LPC55S16"/>
+    <definition extID="platform.drivers.lpc_iocon.LPC55S16"/>
+    <definition extID="platform.drivers.lpc_gpio.LPC55S16"/>
+    <definition extID="platform.drivers.inputmux.LPC55S16"/>
+    <definition extID="platform.drivers.clock.LPC55S16"/>
+    <definition extID="device.LPC55S16_CMSIS.LPC55S16"/>
+    <definition extID="device.LPC55S16_startup.LPC55S16"/>
+    <definition extID="platform.drivers.flexcomm_usart.LPC55S16"/>
+    <definition extID="platform.drivers.flexcomm.LPC55S16"/>
+    <definition extID="component.usart_adapter.LPC55S16"/>
+    <definition extID="component.lists.LPC55S16"/>
+    <definition extID="platform.drivers.reset.LPC55S16"/>
+    <definition extID="CMSIS_Include_core_cm.LPC55S16"/>
+    <definition extID="platform.drivers.inputmux_connections.LPC55S16"/>
+    <definition extID="platform.utilities.misc_utilities.LPC55S16"/>
+    <definition extID="device.LPC55S16_system.LPC55S16"/>
+    <definition extID="iar"/>
+    <definition extID="mdk"/>
+    <definition extID="armgcc"/>
+    <definition extID="mcuxpresso"/>
+    <definition extID="com.nxp.mcuxpresso"/>
+  </externalDefinitions>
+  <example id="lpcxpresso55s16_i2c_dma_b2b_transfer_master" name="i2c_dma_b2b_transfer_master" dependency="utility.debug_console_lite.LPC55S16 platform.utilities.assert_lite.LPC55S16 platform.drivers.lpc_dma.LPC55S16 platform.drivers.flexcomm_i2c.LPC55S16 platform.drivers.flexcomm_i2c_dma.LPC55S16 platform.drivers.common.LPC55S16 platform.drivers.power.LPC55S16 platform.drivers.lpc_iocon.LPC55S16 platform.drivers.lpc_gpio.LPC55S16 platform.drivers.inputmux.LPC55S16 platform.drivers.clock.LPC55S16 device.LPC55S16_CMSIS.LPC55S16 device.LPC55S16_startup.LPC55S16 platform.drivers.flexcomm_usart.LPC55S16 platform.drivers.flexcomm.LPC55S16 component.usart_adapter.LPC55S16 component.lists.LPC55S16 platform.drivers.reset.LPC55S16 CMSIS_Include_core_cm.LPC55S16 platform.drivers.inputmux_connections.LPC55S16 platform.utilities.misc_utilities.LPC55S16 device.LPC55S16_system.LPC55S16" category="driver_examples/i2c">
+    <projects>
+      <project type="com.crt.advproject.projecttype.exe" nature="org.eclipse.cdt.core.cnature"/>
+    </projects>
+    <toolchainSettings>
+      <toolchainSetting id_refs="com.nxp.mcuxpresso">
+        <option id="gnu.c.compiler.option.preprocessor.def.symbols" type="stringList">
+          <value>CPU_LPC55S16JBD100</value>
+          <value>MCUXPRESSO_SDK</value>
+        </option>
+        <option id="com.crt.advproject.gas.fpu" type="enum">
+          <value>com.crt.advproject.gas.fpu.fpv5sp.hard</value>
+        </option>
+        <option id="com.crt.advproject.gcc.fpu" type="enum">
+          <value>com.crt.advproject.gcc.fpu.fpv5sp.hard</value>
+        </option>
+        <option id="gnu.c.compiler.option.optimization.flags" type="string">
+          <value>-fno-common</value>
+        </option>
+        <option id="com.crt.advproject.c.misc.dialect" type="enum">
+          <value>com.crt.advproject.misc.dialect.gnu99</value>
+        </option>
+        <option id="gnu.c.compiler.option.misc.other" type="string">
+          <value>-mcpu=cortex-m33 -c -ffunction-sections -fdata-sections -ffreestanding -fno-builtin</value>
+        </option>
+        <option id="gnu.c.compiler.option.warnings.allwarn" type="boolean">
+          <value>false</value>
+        </option>
+        <option id="com.crt.advproject.link.fpu" type="enum">
+          <value>com.crt.advproject.link.fpu.fpv5sp.hard</value>
+        </option>
+        <option id="gnu.c.link.option.nostdlibs" type="boolean">
+          <value>true</value>
+        </option>
+      </toolchainSetting>
+    </toolchainSettings>
+    <include_paths>
+      <include_path path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/master" project_relative_path="board" type="c_include"/>
+    </include_paths>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/master/iar" project_relative_path="./" type="workspace" toolchain="iar">
+      <files mask="i2c_dma_b2b_transfer_master.ewd"/>
+      <files mask="i2c_dma_b2b_transfer_master.ewp"/>
+      <files mask="i2c_dma_b2b_transfer_master.eww"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/master/mdk" project_relative_path="./" type="workspace" toolchain="mdk">
+      <files mask="i2c_dma_b2b_transfer_master.uvprojx"/>
+      <files mask="i2c_dma_b2b_transfer_master.uvoptx"/>
+      <files mask="JLinkSettings.JLinkScript"/>
+      <files mask="JLinkSettings.ini"/>
+      <files mask="i2c_dma_b2b_transfer_master.uvmpw"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/master/armgcc" project_relative_path="./" type="workspace" toolchain="armgcc">
+      <files mask="build_all.bat"/>
+      <files mask="build_all.sh"/>
+      <files mask="clean.bat"/>
+      <files mask="clean.sh"/>
+      <files mask="CMakeLists.txt"/>
+      <files mask="flags.cmake"/>
+      <files mask="config.cmake"/>
+      <files mask="build_debug.bat"/>
+      <files mask="build_debug.sh"/>
+      <files mask="build_release.bat"/>
+      <files mask="build_release.sh"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/master" project_relative_path="source" type="src">
+      <files mask="i2c_dma_b2b_transfer_master.c"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/master" project_relative_path="board" type="src">
+      <files mask="pin_mux.c"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/master" project_relative_path="board" type="c_include">
+      <files mask="pin_mux.h"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/master" project_relative_path="board" type="src">
+      <files mask="board.c"/>
+      <files mask="clock_config.c"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/master" project_relative_path="board" type="c_include">
+      <files mask="board.h"/>
+      <files mask="clock_config.h"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/master" project_relative_path="doc" type="doc" toolchain="iar mdk mcuxpresso armgcc">
+      <files mask="readme.txt"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/master/iar" project_relative_path="LPC55S16/iar" type="linker" toolchain="iar">
+      <files mask="LPC55S16_flash.icf"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/master/mdk" project_relative_path="LPC55S16/arm" type="linker" toolchain="mdk">
+      <files mask="LPC55S16_flash.scf"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/master/armgcc" project_relative_path="LPC55S16/gcc" type="linker" toolchain="armgcc">
+      <files mask="LPC55S16_flash.ld"/>
+    </source>
+  </example>
+</ksdk:examples>

example_code/i2c/dma_b2b_transfer/master/pin_mux.c

@@ -0,0 +1,133 @@
+/*
+ * Copyright 2017-2020 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: LPC55S16
+package_id: LPC55S16JBD100
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_iocon.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29,
+    mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: inactive, slew_rate: standard,
+    invert: disabled, open_drain: disabled}
+  - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: inactive,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 */
+void BOARD_InitPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    const uint32_t port0_pin29_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
+                                         IOCON_PIO_FUNC1 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, 0U, 29U, port0_pin29_config);
+
+    const uint32_t port0_pin30_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
+                                         IOCON_PIO_FUNC1 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, 0U, 30U, port0_pin30_config);
+
+    const uint32_t port1_pin20_config = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */
+                                         IOCON_PIO_FUNC5 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, 1U, 20U, port1_pin20_config);
+
+    const uint32_t port1_pin21_config = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */
+                                         IOCON_PIO_FUNC5 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, 1U, 21U, port1_pin21_config);
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/

example_code/i2c/dma_b2b_transfer/master/pin_mux.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright 2017-2020 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC1 0x01u         /*!<@brief Selects pin function 1 */
+#define IOCON_PIO_FUNC5 0x05u         /*!<@brief Selects pin function 5 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u    /*!<@brief No addition pin function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/

example_code/i2c/dma_b2b_transfer/master/readme.txt

@@ -0,0 +1,69 @@
+Overview
+========
+The i2c_dma_b2b_transfer_master example shows how to use i2c driver as master to do board to board transfer 
+with DMA:
+
+In this example, one i2c instance as master and another i2c instance on the other board as slave. Master sends a 
+piece of data to slave, and receive a piece of data from slave. This example checks if the data received from 
+slave is correct.
+
+Toolchain supported
+===================
+- IAR embedded Workbench  9.10.2
+- Keil MDK  5.34
+- GCC ARM Embedded  10.2.1
+- MCUXpresso  11.5.0
+
+Hardware requirements
+=====================
+- Micro USB cable
+- Two LPCXpresso55S16 boards
+- Personal Computer
+
+Board settings
+==============
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+MASTER_BOARD        CONNECTS TO         SLAVE_BOARD
+Pin Name   Board Location     Pin Name   Board Location
+I2C_SCL    J9-2               I2C_SCL    J9-2
+I2C_SDA    J9-4               I2C_SDA    J9-4
+GND        J9-8               GND        J9-8    
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The jumper setting:
+    Default jumpers configuration does not work,  you will need to add JP20 and JP21 (JP22 optional for ADC use)
+    
+Prepare the Demo
+================
+1. Connect a micro USB cable between the PC host and the LPC-Link USB port (J1) on the board.
+2. Open a serial terminal on PC for JLink serial device with these settings:
+   - 115200 baud rate
+   - 8 data bits
+   - No parity
+   - One stop bit
+   - No flow control
+3. Download the program to the target board.
+4. Either press the reset button on your board or launch the debugger in your IDE to begin running
+   the demo.
+
+Running the demo
+================
+The following message shows in the terminal if the example runs successfully.
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+I2C board2board DMA example -- Master transfer.
+Master will send data :
+0x 0  0x 1  0x 2  0x 3  0x 4  0x 5  0x 6  0x 7  
+0x 8  0x 9  0x a  0x b  0x c  0x d  0x e  0x f  
+0x10  0x11  0x12  0x13  0x14  0x15  0x16  0x17  
+0x18  0x19  0x1a  0x1b  0x1c  0x1d  0x1e  0x1f  
+
+Receive sent data from slave :
+0x 0  0x 1  0x 2  0x 3  0x 4  0x 5  0x 6  0x 7  
+0x 8  0x 9  0x a  0x b  0x c  0x d  0x e  0x f  
+0x10  0x11  0x12  0x13  0x14  0x15  0x16  0x17  
+0x18  0x19  0x1a  0x1b  0x1c  0x1d  0x1e  0x1f  
+
+
+End of I2C example .
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~

example_code/i2c/dma_b2b_transfer/slave/board.c

@@ -0,0 +1,122 @@
+/*
+ * Copyright 2017-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "board.h"
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+#include "fsl_i2c.h"
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+    /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
+    CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+
+    RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST);
+
+    uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+
+    DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz)
+{
+    i2c_master_config_t i2cConfig = {0};
+
+    I2C_MasterGetDefaultConfig(&i2cConfig);
+    I2C_MasterInit(base, &i2cConfig, clkSrc_Hz);
+}
+
+status_t BOARD_I2C_Send(I2C_Type *base,
+                        uint8_t deviceAddress,
+                        uint32_t subAddress,
+                        uint8_t subaddressSize,
+                        uint8_t *txBuff,
+                        uint8_t txBuffSize)
+{
+    i2c_master_transfer_t masterXfer;
+
+    /* Prepare transfer structure. */
+    masterXfer.slaveAddress   = deviceAddress;
+    masterXfer.direction      = kI2C_Write;
+    masterXfer.subaddress     = subAddress;
+    masterXfer.subaddressSize = subaddressSize;
+    masterXfer.data           = txBuff;
+    masterXfer.dataSize       = txBuffSize;
+    masterXfer.flags          = kI2C_TransferDefaultFlag;
+
+    return I2C_MasterTransferBlocking(base, &masterXfer);
+}
+
+status_t BOARD_I2C_Receive(I2C_Type *base,
+                           uint8_t deviceAddress,
+                           uint32_t subAddress,
+                           uint8_t subaddressSize,
+                           uint8_t *rxBuff,
+                           uint8_t rxBuffSize)
+{
+    i2c_master_transfer_t masterXfer;
+
+    /* Prepare transfer structure. */
+    masterXfer.slaveAddress   = deviceAddress;
+    masterXfer.subaddress     = subAddress;
+    masterXfer.subaddressSize = subaddressSize;
+    masterXfer.data           = rxBuff;
+    masterXfer.dataSize       = rxBuffSize;
+    masterXfer.direction      = kI2C_Read;
+    masterXfer.flags          = kI2C_TransferDefaultFlag;
+
+    return I2C_MasterTransferBlocking(base, &masterXfer);
+}
+
+void BOARD_Accel_I2C_Init(void)
+{
+    BOARD_I2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
+{
+    uint8_t data = (uint8_t)txBuff;
+
+    return BOARD_I2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
+}
+
+status_t BOARD_Accel_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+    return BOARD_I2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
+}
+
+void BOARD_Codec_I2C_Init(void)
+{
+    BOARD_I2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Codec_I2C_Send(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
+{
+    return BOARD_I2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
+                          txBuffSize);
+}
+
+status_t BOARD_Codec_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+    return BOARD_I2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
+}
+#endif /* SDK_I2C_BASED_COMPONENT_USED */

example_code/i2c/dma_b2b_transfer/slave/board.h

@@ -0,0 +1,230 @@
+/*
+ * Copyright 2017-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "clock_config.h"
+#include "fsl_common.h"
+#include "fsl_reset.h"
+#include "fsl_gpio.h"
+#include "fsl_iocon.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "LPCXpresso55S16"
+
+/*! @brief The UART to use for debug messages. */
+/* TODO: rename UART to USART */
+#define BOARD_DEBUG_UART_TYPE       kSerialPort_Uart
+#define BOARD_DEBUG_UART_BASEADDR   (uint32_t) USART0
+#define BOARD_DEBUG_UART_INSTANCE   0U
+#define BOARD_DEBUG_UART_CLK_FREQ   12000000U
+#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM0
+#define BOARD_DEBUG_UART_RST        kFC0_RST_SHIFT_RSTn
+#define BOARD_DEBUG_UART_CLKSRC     kCLOCK_Flexcomm0
+#define BOARD_UART_IRQ_HANDLER      FLEXCOMM0_IRQHandler
+#define BOARD_UART_IRQ              FLEXCOMM0_IRQn
+
+#define BOARD_ACCEL_I2C_BASEADDR   I2C4
+#define BOARD_ACCEL_I2C_CLOCK_FREQ 12000000
+
+#ifndef BOARD_DEBUG_UART_BAUDRATE
+#define BOARD_DEBUG_UART_BAUDRATE 115200U
+#endif /* BOARD_DEBUG_UART_BAUDRATE */
+
+#define BOARD_CODEC_I2C_BASEADDR   I2C4
+#define BOARD_CODEC_I2C_CLOCK_FREQ 12000000
+#define BOARD_CODEC_I2C_INSTANCE   4
+#ifndef BOARD_LED_RED_GPIO
+#define BOARD_LED_RED_GPIO GPIO
+#endif
+#define BOARD_LED_RED_GPIO_PORT 1U
+#ifndef BOARD_LED_RED_GPIO_PIN
+#define BOARD_LED_RED_GPIO_PIN 4U
+#endif
+
+#ifndef BOARD_LED_BLUE_GPIO
+#define BOARD_LED_BLUE_GPIO GPIO
+#endif
+#define BOARD_LED_BLUE_GPIO_PORT 1U
+#ifndef BOARD_LED_BLUE_GPIO_PIN
+#define BOARD_LED_BLUE_GPIO_PIN 6U
+#endif
+
+#ifndef BOARD_LED_GREEN_GPIO
+#define BOARD_LED_GREEN_GPIO GPIO
+#endif
+#define BOARD_LED_GREEN_GPIO_PORT 1U
+#ifndef BOARD_LED_GREEN_GPIO_PIN
+#define BOARD_LED_GREEN_GPIO_PIN 7U
+#endif
+
+#ifndef BOARD_SW1_GPIO
+#define BOARD_SW1_GPIO GPIO
+#endif
+#define BOARD_SW1_GPIO_PORT 1U
+#ifndef BOARD_SW1_GPIO_PIN
+#define BOARD_SW1_GPIO_PIN 18U
+#endif
+#define BOARD_SW1_NAME        "SW1"
+#define BOARD_SW1_IRQ         PIN_INT1_IRQn
+#define BOARD_SW1_IRQ_HANDLER PIN_INT1_IRQHandler
+
+#ifndef BOARD_SW3_GPIO
+#define BOARD_SW3_GPIO GPIO
+#endif
+#define BOARD_SW3_GPIO_PORT 1U
+#ifndef BOARD_SW3_GPIO_PIN
+#define BOARD_SW3_GPIO_PIN 9U
+#endif
+#define BOARD_SW3_NAME              "SW3"
+#define BOARD_SW3_IRQ               PIN_INT1_IRQn
+#define BOARD_SW3_IRQ_HANDLER       PIN_INT1_IRQHandler
+#define BOARD_SW3_GPIO_PININT_INDEX 1
+
+#ifndef BOARD_SW4_GPIO
+#define BOARD_SW4_GPIO GPIO
+#endif
+#define BOARD_SW4_GPIO_PORT 0U
+#ifndef BOARD_SW4_GPIO_PIN
+#define BOARD_SW4_GPIO_PIN 5U
+#endif
+#define BOARD_SW4_NAME              "SW4"
+#define BOARD_SW4_IRQ               PIN_INT0_IRQn
+#define BOARD_SW4_IRQ_HANDLER       PIN_INT0_IRQHandler
+#define BOARD_SW4_GPIO_PININT_INDEX 1
+
+/* USB PHY condfiguration */
+#define BOARD_USB_PHY_D_CAL     (0x05U)
+#define BOARD_USB_PHY_TXCAL45DP (0x0AU)
+#define BOARD_USB_PHY_TXCAL45DM (0x0AU)
+
+#define BOARD_SDIF_BASEADDR       SDIF
+#define BOARD_SDIF_CLKSRC         kCLOCK_SDio
+#define BOARD_SDIF_CLK_FREQ       CLOCK_GetSdioClkFreq()
+#define BOARD_SDIF_CLK_ATTACH     kMAIN_CLK_to_SDIO_CLK
+#define BOARD_SDIF_IRQ            SDIO_IRQn
+#define BOARD_MMC_VCC_SUPPLY      kMMC_VoltageWindows270to360
+#define BOARD_SD_CARD_DETECT_PIN  17
+#define BOARD_SD_CARD_DETECT_PORT 0
+#define BOARD_SD_CARD_DETECT_GPIO GPIO
+#define BOARD_SD_DETECT_TYPE      kSDMMCHOST_DetectCardByHostCD
+
+#define BOARD_SDIF_CD_GPIO_INIT()                                                                    \
+    {                                                                                                \
+        CLOCK_EnableClock(kCLOCK_Gpio2);                                                             \
+        GPIO_PinInit(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN, \
+                     &(gpio_pin_config_t){kGPIO_DigitalInput, 0U});                                  \
+    }
+#define BOARD_SDIF_CD_STATUS() \
+    GPIO_PinRead(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN)
+
+/* Board led color mapping */
+#define LOGIC_LED_ON  1U
+#define LOGIC_LED_OFF 0U
+
+#define BOARD_SDIF_CLK_ATTACH kMAIN_CLK_to_SDIO_CLK
+
+#define LED_RED_INIT(output)                                                                          \
+    {                                                                                                 \
+        IOCON_PinMuxSet(IOCON, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, IOCON_DIGITAL_EN);    \
+        GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN,             \
+                     &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \
+    }
+#define LED_RED_OFF()                                           \
+    GPIO_PortClear(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+                   1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED1 */
+#define LED_RED_ON()                                                                        \
+    GPIO_PortSet(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT,                               \
+                 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED1 \ \ \ \ \ \ \ \ \ \ \
+                                                */
+#define LED_RED_TOGGLE()                                         \
+    GPIO_PortToggle(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+                    1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED1 */
+
+#define LED_BLUE_INIT(output)                                                                         \
+    {                                                                                                 \
+        IOCON_PinMuxSet(IOCON, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, IOCON_DIGITAL_EN);  \
+        GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN,          \
+                     &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \
+    }
+#define LED_BLUE_OFF()                                            \
+    GPIO_PortClear(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                   1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED1 */
+#define LED_BLUE_ON()                                           \
+    GPIO_PortSet(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED1 */
+#define LED_BLUE_TOGGLE()                                          \
+    GPIO_PortToggle(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                    1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED1 */
+
+#define LED_GREEN_INIT(output)                                                              \
+    GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, BOARD_LED_GREEN_GPIO_PIN, \
+                 &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED1 */
+#define LED_GREEN_OFF()                                             \
+    GPIO_PortClear(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                   1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED1 */
+#define LED_GREEN_ON()                                            \
+    GPIO_PortSet(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED1 */
+#define LED_GREEN_TOGGLE()                                           \
+    GPIO_PortToggle(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                    1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED1 */
+
+/* Display. */
+#define BOARD_LCD_DC_GPIO      GPIO
+#define BOARD_LCD_DC_GPIO_PORT 1U
+#define BOARD_LCD_DC_GPIO_PIN  5U
+
+/* Serial MWM WIFI */
+#define BOARD_SERIAL_MWM_PORT_CLK_FREQ CLOCK_GetFlexCommClkFreq(2)
+#define BOARD_SERIAL_MWM_PORT          USART2
+#define BOARD_SERIAL_MWM_PORT_IRQn     FLEXCOMM2_IRQn
+#define BOARD_SERIAL_MWM_RST_WRITE(output)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz);
+status_t BOARD_I2C_Send(I2C_Type *base,
+                        uint8_t deviceAddress,
+                        uint32_t subAddress,
+                        uint8_t subaddressSize,
+                        uint8_t *txBuff,
+                        uint8_t txBuffSize);
+status_t BOARD_I2C_Receive(I2C_Type *base,
+                           uint8_t deviceAddress,
+                           uint32_t subAddress,
+                           uint8_t subaddressSize,
+                           uint8_t *rxBuff,
+                           uint8_t rxBuffSize);
+void BOARD_Accel_I2C_Init(void);
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
+status_t BOARD_Accel_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+void BOARD_Codec_I2C_Init(void);
+status_t BOARD_Codec_I2C_Send(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
+status_t BOARD_Codec_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */

example_code/i2c/dma_b2b_transfer/slave/clock_config.c

@@ -0,0 +1,380 @@
+/*
+ * Copyright 2017-2018 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to set up clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up wait states of the flash.
+ *
+ * 3. Set up all dividers.
+ *
+ * 4. Set up all selectors to provide selected clocks.
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v7.0
+processor: LPC55S16
+package_id: LPC55S16JBD100
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+board: LPCXpresso55S16
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockPLL150M();
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 12 MHz}
+settings:
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    POWER_SetVoltageForFreq(12000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(12000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO12M */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF96M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF96M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    POWER_SetVoltageForFreq(96000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(96000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL100M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 100 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
+- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
+- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL100M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable High speed Crystal oscillator output to system  */
+
+    POWER_SetVoltageForFreq(100000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(100000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U),
+        .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
+        .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
+        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+        .pllRate = 100000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL150M
+called_from_default_init: true
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 150 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true}
+- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true}
+- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true}
+sources:
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL150M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable High speed Crystal oscillator output to system  */
+
+    POWER_SetVoltageForFreq(150000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(150000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
+        .pllndec = SYSCON_PLL0NDEC_NDIV(8U),
+        .pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
+        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+        .pllRate = 150000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockPLL1_150M ********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL1_150M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 150 MHz}
+settings:
+- {id: PLL1_Mode, value: Normal}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS}
+- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL1M_MULT.scale, value: '150', locked: true}
+- {id: SYSCON.PLL1N_DIV.scale, value: '8', locked: true}
+- {id: SYSCON.PLL1_PDEC.scale, value: '2', locked: true}
+sources:
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL1_150M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable High speed Crystal oscillator output to system  */
+
+    POWER_SetVoltageForFreq(150000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(150000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL1 */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL1);                    /*!< Switch PLL1CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL1);                  /* Ensure PLL is on  */
+    const pll_setup_t pll1Setup = {
+        .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(53U) | SYSCON_PLL1CTRL_SELP(31U),
+        .pllndec = SYSCON_PLL1NDEC_NDIV(8U),
+        .pllpdec = SYSCON_PLL1PDEC_PDIV(1U),
+        .pllmdec = SYSCON_PLL1MDEC_MDIV(150U),
+        .pllRate = 150000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL1Freq(&pll1Setup);                        /*!< Configure PLL1 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL1_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL1 */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK;
+#endif
+}
+

example_code/i2c/dma_b2b_transfer/slave/clock_config.h

@@ -0,0 +1,173 @@
+/*
+ * Copyright 2017-2018 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         16000000U  /*!< Board xtal frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK         96000000U  /*!< Core clock frequency: 96000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF96M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL100M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         150000000U  /*!< Core clock frequency: 150000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockPLL1_150M ********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK       150000000U  /*!< Core clock frequency: 150000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL1_150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+

example_code/i2c/dma_b2b_transfer/slave/i2c_dma_b2b_transfer_slave.c

@@ -0,0 +1,148 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*  SDK Included Files */
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_debug_console.h"
+#include "fsl_i2c.h"
+
+#include "fsl_power.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define EXAMPLE_I2C_SLAVE_BASE    (I2C4_BASE)
+#define I2C_SLAVE_CLOCK_FREQUENCY (12000000)
+
+
+#define EXAMPLE_I2C_SLAVE ((I2C_Type *)EXAMPLE_I2C_SLAVE_BASE)
+
+#define I2C_MASTER_SLAVE_ADDR_7BIT (0x7EU)
+#define I2C_DATA_LENGTH            (34) /* MAX is 256 */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+uint8_t g_slave_buff[I2C_DATA_LENGTH];
+i2c_slave_handle_t g_s_handle;
+volatile bool g_SlaveCompletionFlag = false;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static void i2c_slave_callback(I2C_Type *base, volatile i2c_slave_transfer_t *xfer, void *userData)
+{
+    switch (xfer->event)
+    {
+        /*  Address match event */
+        case kI2C_SlaveAddressMatchEvent:
+            xfer->rxData = NULL;
+            xfer->rxSize = 0;
+            break;
+        /*  Receive request */
+        case kI2C_SlaveReceiveEvent:
+            xfer->rxData = g_slave_buff;
+            xfer->rxSize = I2C_DATA_LENGTH;
+            break;
+
+        /*  Transfer done */
+        case kI2C_SlaveCompletionEvent:
+            /*  Transmit request */
+            g_SlaveCompletionFlag = true;
+            break;
+
+        /*  Transmit request */
+        case kI2C_SlaveTransmitEvent:
+            xfer->txData = &g_slave_buff[2];
+            xfer->txSize = g_slave_buff[1];
+            break;
+
+        default:
+            g_SlaveCompletionFlag = false;
+            break;
+    }
+}
+
+int main(void)
+{
+    i2c_slave_config_t slaveConfig;
+
+    /* set BOD VBAT level to 1.65V */
+    POWER_SetBodVbatLevel(kPOWER_BodVbatLevel1650mv, kPOWER_BodHystLevel50mv, false);
+    /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
+    CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+
+    /* attach 12 MHz clock to FLEXCOMM4 (I2C master) */
+    CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
+
+    /* reset FLEXCOMM for I2C */
+    RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn);
+
+    BOARD_InitBootPins();
+    BOARD_InitBootClocks();
+    BOARD_InitDebugConsole();
+
+    PRINTF("\r\nI2C board2board DMA example -- Slave transfer.\r\n\r\n");
+
+    /*Set up i2c slave first*/
+    /*
+     * slaveConfig.addressingMode = kI2C_Address7bit;
+     * slaveConfig.enableGeneralCall = false;
+     * slaveConfig.enableWakeUp = false;
+     * slaveConfig.enableBaudRateCtl = false;
+     * slaveConfig.enableSlave = true;
+     */
+    I2C_SlaveGetDefaultConfig(&slaveConfig);
+
+    /* Change the slave address */
+    slaveConfig.address0.address = I2C_MASTER_SLAVE_ADDR_7BIT;
+
+    /* Initialize the I2C slave peripheral */
+    I2C_SlaveInit(EXAMPLE_I2C_SLAVE, &slaveConfig, I2C_SLAVE_CLOCK_FREQUENCY);
+
+    memset(g_slave_buff, 0, sizeof(g_slave_buff));
+    memset(&g_s_handle, 0, sizeof(g_s_handle));
+
+    I2C_SlaveTransferCreateHandle(EXAMPLE_I2C_SLAVE, &g_s_handle, i2c_slave_callback, NULL);
+    I2C_SlaveTransferNonBlocking(EXAMPLE_I2C_SLAVE, &g_s_handle,
+                                 kI2C_SlaveCompletionEvent | kI2C_SlaveAddressMatchEvent);
+
+    /*  wait for transfer completed. */
+    while (!g_SlaveCompletionFlag)
+    {
+    }
+    g_SlaveCompletionFlag = false;
+
+    PRINTF("Slave received data :");
+    for (uint32_t i = 0U; i < g_slave_buff[1]; i++)
+    {
+        if (i % 8 == 0)
+        {
+            PRINTF("\r\n");
+        }
+        PRINTF("0x%2x  ", g_slave_buff[2 + i]);
+    }
+    PRINTF("\r\n\r\n");
+
+    /* Wait for master receive completed.*/
+    while (!g_SlaveCompletionFlag)
+    {
+    }
+    g_SlaveCompletionFlag = false;
+
+    PRINTF("\r\nEnd of I2C example .\r\n");
+
+    while (1)
+    {
+    }
+}

example_code/i2c/dma_b2b_transfer/slave/i2c_dma_b2b_transfer_slave_v3_9.xml

@@ -0,0 +1,124 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<ksdk:examples xmlns:ksdk="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd manifest.xsd">
+  <externalDefinitions>
+    <definition extID="utility.debug_console_lite.LPC55S16"/>
+    <definition extID="platform.utilities.assert_lite.LPC55S16"/>
+    <definition extID="platform.drivers.flexcomm_i2c.LPC55S16"/>
+    <definition extID="platform.drivers.common.LPC55S16"/>
+    <definition extID="platform.drivers.power.LPC55S16"/>
+    <definition extID="platform.drivers.lpc_iocon.LPC55S16"/>
+    <definition extID="platform.drivers.lpc_gpio.LPC55S16"/>
+    <definition extID="platform.drivers.inputmux.LPC55S16"/>
+    <definition extID="platform.drivers.clock.LPC55S16"/>
+    <definition extID="device.LPC55S16_CMSIS.LPC55S16"/>
+    <definition extID="device.LPC55S16_startup.LPC55S16"/>
+    <definition extID="platform.drivers.flexcomm_usart.LPC55S16"/>
+    <definition extID="platform.drivers.flexcomm.LPC55S16"/>
+    <definition extID="component.usart_adapter.LPC55S16"/>
+    <definition extID="component.lists.LPC55S16"/>
+    <definition extID="platform.drivers.reset.LPC55S16"/>
+    <definition extID="CMSIS_Include_core_cm.LPC55S16"/>
+    <definition extID="platform.drivers.inputmux_connections.LPC55S16"/>
+    <definition extID="platform.utilities.misc_utilities.LPC55S16"/>
+    <definition extID="device.LPC55S16_system.LPC55S16"/>
+    <definition extID="iar"/>
+    <definition extID="mdk"/>
+    <definition extID="armgcc"/>
+    <definition extID="mcuxpresso"/>
+    <definition extID="com.nxp.mcuxpresso"/>
+  </externalDefinitions>
+  <example id="lpcxpresso55s16_i2c_dma_b2b_transfer_slave" name="i2c_dma_b2b_transfer_slave" dependency="utility.debug_console_lite.LPC55S16 platform.utilities.assert_lite.LPC55S16 platform.drivers.flexcomm_i2c.LPC55S16 platform.drivers.common.LPC55S16 platform.drivers.power.LPC55S16 platform.drivers.lpc_iocon.LPC55S16 platform.drivers.lpc_gpio.LPC55S16 platform.drivers.inputmux.LPC55S16 platform.drivers.clock.LPC55S16 device.LPC55S16_CMSIS.LPC55S16 device.LPC55S16_startup.LPC55S16 platform.drivers.flexcomm_usart.LPC55S16 platform.drivers.flexcomm.LPC55S16 component.usart_adapter.LPC55S16 component.lists.LPC55S16 platform.drivers.reset.LPC55S16 CMSIS_Include_core_cm.LPC55S16 platform.drivers.inputmux_connections.LPC55S16 platform.utilities.misc_utilities.LPC55S16 device.LPC55S16_system.LPC55S16" category="driver_examples/i2c">
+    <projects>
+      <project type="com.crt.advproject.projecttype.exe" nature="org.eclipse.cdt.core.cnature"/>
+    </projects>
+    <toolchainSettings>
+      <toolchainSetting id_refs="com.nxp.mcuxpresso">
+        <option id="gnu.c.compiler.option.preprocessor.def.symbols" type="stringList">
+          <value>CPU_LPC55S16JBD100</value>
+          <value>MCUXPRESSO_SDK</value>
+        </option>
+        <option id="com.crt.advproject.gas.fpu" type="enum">
+          <value>com.crt.advproject.gas.fpu.fpv5sp.hard</value>
+        </option>
+        <option id="com.crt.advproject.gcc.fpu" type="enum">
+          <value>com.crt.advproject.gcc.fpu.fpv5sp.hard</value>
+        </option>
+        <option id="gnu.c.compiler.option.optimization.flags" type="string">
+          <value>-fno-common</value>
+        </option>
+        <option id="com.crt.advproject.c.misc.dialect" type="enum">
+          <value>com.crt.advproject.misc.dialect.gnu99</value>
+        </option>
+        <option id="gnu.c.compiler.option.misc.other" type="string">
+          <value>-mcpu=cortex-m33 -c -ffunction-sections -fdata-sections -ffreestanding -fno-builtin</value>
+        </option>
+        <option id="gnu.c.compiler.option.warnings.allwarn" type="boolean">
+          <value>false</value>
+        </option>
+        <option id="com.crt.advproject.link.fpu" type="enum">
+          <value>com.crt.advproject.link.fpu.fpv5sp.hard</value>
+        </option>
+        <option id="gnu.c.link.option.nostdlibs" type="boolean">
+          <value>true</value>
+        </option>
+      </toolchainSetting>
+    </toolchainSettings>
+    <include_paths>
+      <include_path path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/slave" project_relative_path="board" type="c_include"/>
+    </include_paths>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/slave/iar" project_relative_path="./" type="workspace" toolchain="iar">
+      <files mask="i2c_dma_b2b_transfer_slave.ewd"/>
+      <files mask="i2c_dma_b2b_transfer_slave.ewp"/>
+      <files mask="i2c_dma_b2b_transfer_slave.eww"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/slave/mdk" project_relative_path="./" type="workspace" toolchain="mdk">
+      <files mask="i2c_dma_b2b_transfer_slave.uvprojx"/>
+      <files mask="i2c_dma_b2b_transfer_slave.uvoptx"/>
+      <files mask="JLinkSettings.JLinkScript"/>
+      <files mask="JLinkSettings.ini"/>
+      <files mask="i2c_dma_b2b_transfer_slave.uvmpw"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/slave/armgcc" project_relative_path="./" type="workspace" toolchain="armgcc">
+      <files mask="build_all.bat"/>
+      <files mask="build_all.sh"/>
+      <files mask="clean.bat"/>
+      <files mask="clean.sh"/>
+      <files mask="CMakeLists.txt"/>
+      <files mask="flags.cmake"/>
+      <files mask="config.cmake"/>
+      <files mask="build_debug.bat"/>
+      <files mask="build_debug.sh"/>
+      <files mask="build_release.bat"/>
+      <files mask="build_release.sh"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/slave" project_relative_path="source" type="src">
+      <files mask="i2c_dma_b2b_transfer_slave.c"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/slave" project_relative_path="board" type="src">
+      <files mask="pin_mux.c"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/slave" project_relative_path="board" type="c_include">
+      <files mask="pin_mux.h"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/slave" project_relative_path="board" type="src">
+      <files mask="board.c"/>
+      <files mask="clock_config.c"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/slave" project_relative_path="board" type="c_include">
+      <files mask="board.h"/>
+      <files mask="clock_config.h"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/slave" project_relative_path="doc" type="doc" toolchain="iar mdk mcuxpresso armgcc">
+      <files mask="readme.txt"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/slave/iar" project_relative_path="LPC55S16/iar" type="linker" toolchain="iar">
+      <files mask="LPC55S16_flash.icf"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/slave/mdk" project_relative_path="LPC55S16/arm" type="linker" toolchain="mdk">
+      <files mask="LPC55S16_flash.scf"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/dma_b2b_transfer/slave/armgcc" project_relative_path="LPC55S16/gcc" type="linker" toolchain="armgcc">
+      <files mask="LPC55S16_flash.ld"/>
+    </source>
+  </example>
+</ksdk:examples>

example_code/i2c/dma_b2b_transfer/slave/pin_mux.c

@@ -0,0 +1,133 @@
+/*
+ * Copyright 2017-2020 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: LPC55S16
+package_id: LPC55S16JBD100
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_iocon.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29,
+    mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: inactive, slew_rate: standard,
+    invert: disabled, open_drain: disabled}
+  - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: inactive,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 */
+void BOARD_InitPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    const uint32_t port0_pin29_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
+                                         IOCON_PIO_FUNC1 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, 0U, 29U, port0_pin29_config);
+
+    const uint32_t port0_pin30_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
+                                         IOCON_PIO_FUNC1 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, 0U, 30U, port0_pin30_config);
+
+    const uint32_t port1_pin20_config = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */
+                                         IOCON_PIO_FUNC5 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, 1U, 20U, port1_pin20_config);
+
+    const uint32_t port1_pin21_config = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */
+                                         IOCON_PIO_FUNC5 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, 1U, 21U, port1_pin21_config);
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/

example_code/i2c/dma_b2b_transfer/slave/pin_mux.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright 2017-2020 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC1 0x01u         /*!<@brief Selects pin function 1 */
+#define IOCON_PIO_FUNC5 0x05u         /*!<@brief Selects pin function 5 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u    /*!<@brief No addition pin function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/

example_code/i2c/dma_b2b_transfer/slave/readme.txt

@@ -0,0 +1,65 @@
+Overview
+========
+The i2c_dma_b2b_transfer_slave example shows how to use i2c driver as slave to do board to board transfer 
+with a DMA master:
+
+In this example, one i2c instance as slave and another i2c instance on the other board as master. Master sends a 
+piece of data to slave, and receive a piece of data from slave. This example checks if the data received from 
+slave is correct. I2C slave works as supporting board to help demonstrate master DMA trasnfer, actually uses interrupt
+way. 
+
+Toolchain supported
+===================
+- IAR embedded Workbench  9.10.2
+- Keil MDK  5.34
+- GCC ARM Embedded  10.2.1
+- MCUXpresso  11.5.0
+
+Hardware requirements
+=====================
+- Micro USB cable
+- Two LPCXpresso55S16 boards
+- Personal Computer
+
+Board settings
+==============
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+MASTER_BOARD        CONNECTS TO         SLAVE_BOARD
+Pin Name   Board Location     Pin Name   Board Location
+I2C_SCL    J9-2               I2C_SCL    J9-2
+I2C_SDA    J9-4               I2C_SDA    J9-4
+GND        J9-8               GND        J9-8   
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The jumper setting:
+    Default jumpers configuration does not work,  you will need to add JP20 and JP21 (JP22 optional for ADC use)
+    
+Prepare the Demo
+================
+1. Connect a micro USB cable between the PC host and the LPC-Link USB port (J1) on the board.
+2. Open a serial terminal on PC for JLink serial device with these settings:
+   - 115200 baud rate
+   - 8 data bits
+   - No parity
+   - One stop bit
+   - No flow control
+3. Download the program to the target board.
+4. Either press the reset button on your board or launch the debugger in your IDE to begin running
+   the demo.
+
+Running the demo
+================
+The following message shows in the terminal if the example runs successfully.
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+I2C board2board DMA example -- Slave transfer.
+
+Slave received data :
+0x 0  0x 1  0x 2  0x 3  0x 4  0x 5  0x 6  0x 7  
+0x 8  0x 9  0x a  0x b  0x c  0x d  0x e  0x f  
+0x10  0x11  0x12  0x13  0x14  0x15  0x16  0x17  
+0x18  0x19  0x1a  0x1b  0x1c  0x1d  0x1e  0x1f  
+
+
+End of I2C example .
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~

example_code/i2c/interrupt_b2b_transfer/master/board.c

@@ -0,0 +1,122 @@
+/*
+ * Copyright 2017-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "board.h"
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+#include "fsl_i2c.h"
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+    /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
+    CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+
+    RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST);
+
+    uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+
+    DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz)
+{
+    i2c_master_config_t i2cConfig = {0};
+
+    I2C_MasterGetDefaultConfig(&i2cConfig);
+    I2C_MasterInit(base, &i2cConfig, clkSrc_Hz);
+}
+
+status_t BOARD_I2C_Send(I2C_Type *base,
+                        uint8_t deviceAddress,
+                        uint32_t subAddress,
+                        uint8_t subaddressSize,
+                        uint8_t *txBuff,
+                        uint8_t txBuffSize)
+{
+    i2c_master_transfer_t masterXfer;
+
+    /* Prepare transfer structure. */
+    masterXfer.slaveAddress   = deviceAddress;
+    masterXfer.direction      = kI2C_Write;
+    masterXfer.subaddress     = subAddress;
+    masterXfer.subaddressSize = subaddressSize;
+    masterXfer.data           = txBuff;
+    masterXfer.dataSize       = txBuffSize;
+    masterXfer.flags          = kI2C_TransferDefaultFlag;
+
+    return I2C_MasterTransferBlocking(base, &masterXfer);
+}
+
+status_t BOARD_I2C_Receive(I2C_Type *base,
+                           uint8_t deviceAddress,
+                           uint32_t subAddress,
+                           uint8_t subaddressSize,
+                           uint8_t *rxBuff,
+                           uint8_t rxBuffSize)
+{
+    i2c_master_transfer_t masterXfer;
+
+    /* Prepare transfer structure. */
+    masterXfer.slaveAddress   = deviceAddress;
+    masterXfer.subaddress     = subAddress;
+    masterXfer.subaddressSize = subaddressSize;
+    masterXfer.data           = rxBuff;
+    masterXfer.dataSize       = rxBuffSize;
+    masterXfer.direction      = kI2C_Read;
+    masterXfer.flags          = kI2C_TransferDefaultFlag;
+
+    return I2C_MasterTransferBlocking(base, &masterXfer);
+}
+
+void BOARD_Accel_I2C_Init(void)
+{
+    BOARD_I2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
+{
+    uint8_t data = (uint8_t)txBuff;
+
+    return BOARD_I2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
+}
+
+status_t BOARD_Accel_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+    return BOARD_I2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
+}
+
+void BOARD_Codec_I2C_Init(void)
+{
+    BOARD_I2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Codec_I2C_Send(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
+{
+    return BOARD_I2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
+                          txBuffSize);
+}
+
+status_t BOARD_Codec_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+    return BOARD_I2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
+}
+#endif /* SDK_I2C_BASED_COMPONENT_USED */

example_code/i2c/interrupt_b2b_transfer/master/board.h

@@ -0,0 +1,230 @@
+/*
+ * Copyright 2017-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "clock_config.h"
+#include "fsl_common.h"
+#include "fsl_reset.h"
+#include "fsl_gpio.h"
+#include "fsl_iocon.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "LPCXpresso55S16"
+
+/*! @brief The UART to use for debug messages. */
+/* TODO: rename UART to USART */
+#define BOARD_DEBUG_UART_TYPE       kSerialPort_Uart
+#define BOARD_DEBUG_UART_BASEADDR   (uint32_t) USART0
+#define BOARD_DEBUG_UART_INSTANCE   0U
+#define BOARD_DEBUG_UART_CLK_FREQ   12000000U
+#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM0
+#define BOARD_DEBUG_UART_RST        kFC0_RST_SHIFT_RSTn
+#define BOARD_DEBUG_UART_CLKSRC     kCLOCK_Flexcomm0
+#define BOARD_UART_IRQ_HANDLER      FLEXCOMM0_IRQHandler
+#define BOARD_UART_IRQ              FLEXCOMM0_IRQn
+
+#define BOARD_ACCEL_I2C_BASEADDR   I2C4
+#define BOARD_ACCEL_I2C_CLOCK_FREQ 12000000
+
+#ifndef BOARD_DEBUG_UART_BAUDRATE
+#define BOARD_DEBUG_UART_BAUDRATE 115200U
+#endif /* BOARD_DEBUG_UART_BAUDRATE */
+
+#define BOARD_CODEC_I2C_BASEADDR   I2C4
+#define BOARD_CODEC_I2C_CLOCK_FREQ 12000000
+#define BOARD_CODEC_I2C_INSTANCE   4
+#ifndef BOARD_LED_RED_GPIO
+#define BOARD_LED_RED_GPIO GPIO
+#endif
+#define BOARD_LED_RED_GPIO_PORT 1U
+#ifndef BOARD_LED_RED_GPIO_PIN
+#define BOARD_LED_RED_GPIO_PIN 4U
+#endif
+
+#ifndef BOARD_LED_BLUE_GPIO
+#define BOARD_LED_BLUE_GPIO GPIO
+#endif
+#define BOARD_LED_BLUE_GPIO_PORT 1U
+#ifndef BOARD_LED_BLUE_GPIO_PIN
+#define BOARD_LED_BLUE_GPIO_PIN 6U
+#endif
+
+#ifndef BOARD_LED_GREEN_GPIO
+#define BOARD_LED_GREEN_GPIO GPIO
+#endif
+#define BOARD_LED_GREEN_GPIO_PORT 1U
+#ifndef BOARD_LED_GREEN_GPIO_PIN
+#define BOARD_LED_GREEN_GPIO_PIN 7U
+#endif
+
+#ifndef BOARD_SW1_GPIO
+#define BOARD_SW1_GPIO GPIO
+#endif
+#define BOARD_SW1_GPIO_PORT 1U
+#ifndef BOARD_SW1_GPIO_PIN
+#define BOARD_SW1_GPIO_PIN 18U
+#endif
+#define BOARD_SW1_NAME        "SW1"
+#define BOARD_SW1_IRQ         PIN_INT1_IRQn
+#define BOARD_SW1_IRQ_HANDLER PIN_INT1_IRQHandler
+
+#ifndef BOARD_SW3_GPIO
+#define BOARD_SW3_GPIO GPIO
+#endif
+#define BOARD_SW3_GPIO_PORT 1U
+#ifndef BOARD_SW3_GPIO_PIN
+#define BOARD_SW3_GPIO_PIN 9U
+#endif
+#define BOARD_SW3_NAME              "SW3"
+#define BOARD_SW3_IRQ               PIN_INT1_IRQn
+#define BOARD_SW3_IRQ_HANDLER       PIN_INT1_IRQHandler
+#define BOARD_SW3_GPIO_PININT_INDEX 1
+
+#ifndef BOARD_SW4_GPIO
+#define BOARD_SW4_GPIO GPIO
+#endif
+#define BOARD_SW4_GPIO_PORT 0U
+#ifndef BOARD_SW4_GPIO_PIN
+#define BOARD_SW4_GPIO_PIN 5U
+#endif
+#define BOARD_SW4_NAME              "SW4"
+#define BOARD_SW4_IRQ               PIN_INT0_IRQn
+#define BOARD_SW4_IRQ_HANDLER       PIN_INT0_IRQHandler
+#define BOARD_SW4_GPIO_PININT_INDEX 1
+
+/* USB PHY condfiguration */
+#define BOARD_USB_PHY_D_CAL     (0x05U)
+#define BOARD_USB_PHY_TXCAL45DP (0x0AU)
+#define BOARD_USB_PHY_TXCAL45DM (0x0AU)
+
+#define BOARD_SDIF_BASEADDR       SDIF
+#define BOARD_SDIF_CLKSRC         kCLOCK_SDio
+#define BOARD_SDIF_CLK_FREQ       CLOCK_GetSdioClkFreq()
+#define BOARD_SDIF_CLK_ATTACH     kMAIN_CLK_to_SDIO_CLK
+#define BOARD_SDIF_IRQ            SDIO_IRQn
+#define BOARD_MMC_VCC_SUPPLY      kMMC_VoltageWindows270to360
+#define BOARD_SD_CARD_DETECT_PIN  17
+#define BOARD_SD_CARD_DETECT_PORT 0
+#define BOARD_SD_CARD_DETECT_GPIO GPIO
+#define BOARD_SD_DETECT_TYPE      kSDMMCHOST_DetectCardByHostCD
+
+#define BOARD_SDIF_CD_GPIO_INIT()                                                                    \
+    {                                                                                                \
+        CLOCK_EnableClock(kCLOCK_Gpio2);                                                             \
+        GPIO_PinInit(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN, \
+                     &(gpio_pin_config_t){kGPIO_DigitalInput, 0U});                                  \
+    }
+#define BOARD_SDIF_CD_STATUS() \
+    GPIO_PinRead(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN)
+
+/* Board led color mapping */
+#define LOGIC_LED_ON  1U
+#define LOGIC_LED_OFF 0U
+
+#define BOARD_SDIF_CLK_ATTACH kMAIN_CLK_to_SDIO_CLK
+
+#define LED_RED_INIT(output)                                                                          \
+    {                                                                                                 \
+        IOCON_PinMuxSet(IOCON, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, IOCON_DIGITAL_EN);    \
+        GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN,             \
+                     &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \
+    }
+#define LED_RED_OFF()                                           \
+    GPIO_PortClear(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+                   1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED1 */
+#define LED_RED_ON()                                                                        \
+    GPIO_PortSet(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT,                               \
+                 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED1 \ \ \ \ \ \ \ \ \ \ \
+                                                */
+#define LED_RED_TOGGLE()                                         \
+    GPIO_PortToggle(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+                    1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED1 */
+
+#define LED_BLUE_INIT(output)                                                                         \
+    {                                                                                                 \
+        IOCON_PinMuxSet(IOCON, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, IOCON_DIGITAL_EN);  \
+        GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN,          \
+                     &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \
+    }
+#define LED_BLUE_OFF()                                            \
+    GPIO_PortClear(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                   1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED1 */
+#define LED_BLUE_ON()                                           \
+    GPIO_PortSet(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED1 */
+#define LED_BLUE_TOGGLE()                                          \
+    GPIO_PortToggle(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                    1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED1 */
+
+#define LED_GREEN_INIT(output)                                                              \
+    GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, BOARD_LED_GREEN_GPIO_PIN, \
+                 &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED1 */
+#define LED_GREEN_OFF()                                             \
+    GPIO_PortClear(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                   1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED1 */
+#define LED_GREEN_ON()                                            \
+    GPIO_PortSet(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED1 */
+#define LED_GREEN_TOGGLE()                                           \
+    GPIO_PortToggle(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                    1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED1 */
+
+/* Display. */
+#define BOARD_LCD_DC_GPIO      GPIO
+#define BOARD_LCD_DC_GPIO_PORT 1U
+#define BOARD_LCD_DC_GPIO_PIN  5U
+
+/* Serial MWM WIFI */
+#define BOARD_SERIAL_MWM_PORT_CLK_FREQ CLOCK_GetFlexCommClkFreq(2)
+#define BOARD_SERIAL_MWM_PORT          USART2
+#define BOARD_SERIAL_MWM_PORT_IRQn     FLEXCOMM2_IRQn
+#define BOARD_SERIAL_MWM_RST_WRITE(output)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz);
+status_t BOARD_I2C_Send(I2C_Type *base,
+                        uint8_t deviceAddress,
+                        uint32_t subAddress,
+                        uint8_t subaddressSize,
+                        uint8_t *txBuff,
+                        uint8_t txBuffSize);
+status_t BOARD_I2C_Receive(I2C_Type *base,
+                           uint8_t deviceAddress,
+                           uint32_t subAddress,
+                           uint8_t subaddressSize,
+                           uint8_t *rxBuff,
+                           uint8_t rxBuffSize);
+void BOARD_Accel_I2C_Init(void);
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
+status_t BOARD_Accel_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+void BOARD_Codec_I2C_Init(void);
+status_t BOARD_Codec_I2C_Send(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
+status_t BOARD_Codec_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */

example_code/i2c/interrupt_b2b_transfer/master/clock_config.c

@@ -0,0 +1,380 @@
+/*
+ * Copyright 2017-2018 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to set up clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up wait states of the flash.
+ *
+ * 3. Set up all dividers.
+ *
+ * 4. Set up all selectors to provide selected clocks.
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v7.0
+processor: LPC55S16
+package_id: LPC55S16JBD100
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+board: LPCXpresso55S16
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockPLL150M();
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 12 MHz}
+settings:
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    POWER_SetVoltageForFreq(12000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(12000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO12M */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF96M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF96M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    POWER_SetVoltageForFreq(96000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(96000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL100M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 100 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
+- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
+- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL100M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable High speed Crystal oscillator output to system  */
+
+    POWER_SetVoltageForFreq(100000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(100000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U),
+        .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
+        .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
+        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+        .pllRate = 100000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL150M
+called_from_default_init: true
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 150 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true}
+- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true}
+- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true}
+sources:
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL150M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable High speed Crystal oscillator output to system  */
+
+    POWER_SetVoltageForFreq(150000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(150000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
+        .pllndec = SYSCON_PLL0NDEC_NDIV(8U),
+        .pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
+        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+        .pllRate = 150000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockPLL1_150M ********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL1_150M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 150 MHz}
+settings:
+- {id: PLL1_Mode, value: Normal}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS}
+- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL1M_MULT.scale, value: '150', locked: true}
+- {id: SYSCON.PLL1N_DIV.scale, value: '8', locked: true}
+- {id: SYSCON.PLL1_PDEC.scale, value: '2', locked: true}
+sources:
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL1_150M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable High speed Crystal oscillator output to system  */
+
+    POWER_SetVoltageForFreq(150000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(150000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL1 */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL1);                    /*!< Switch PLL1CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL1);                  /* Ensure PLL is on  */
+    const pll_setup_t pll1Setup = {
+        .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(53U) | SYSCON_PLL1CTRL_SELP(31U),
+        .pllndec = SYSCON_PLL1NDEC_NDIV(8U),
+        .pllpdec = SYSCON_PLL1PDEC_PDIV(1U),
+        .pllmdec = SYSCON_PLL1MDEC_MDIV(150U),
+        .pllRate = 150000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL1Freq(&pll1Setup);                        /*!< Configure PLL1 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL1_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL1 */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK;
+#endif
+}
+

example_code/i2c/interrupt_b2b_transfer/master/clock_config.h

@@ -0,0 +1,173 @@
+/*
+ * Copyright 2017-2018 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         16000000U  /*!< Board xtal frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK         96000000U  /*!< Core clock frequency: 96000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF96M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL100M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         150000000U  /*!< Core clock frequency: 150000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockPLL1_150M ********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK       150000000U  /*!< Core clock frequency: 150000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL1_150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+

example_code/i2c/interrupt_b2b_transfer/master/i2c_interrupt_b2b_transfer_master.c

@@ -0,0 +1,202 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*  Standard C Included Files */
+#include <stdio.h>
+#include <string.h>
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_debug_console.h"
+#include "fsl_i2c.h"
+
+#include "fsl_power.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define EXAMPLE_I2C_MASTER_BASE    (I2C4_BASE)
+#define I2C_MASTER_CLOCK_FREQUENCY (12000000)
+#define EXAMPLE_I2C_MASTER ((I2C_Type *)EXAMPLE_I2C_MASTER_BASE)
+
+#define I2C_MASTER_SLAVE_ADDR_7BIT (0x7EU)
+#define I2C_BAUDRATE               (100000) /* 100K */
+#define I2C_DATA_LENGTH            (33)     /* MAX is 256 */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+uint8_t g_master_txBuff[I2C_DATA_LENGTH];
+uint8_t g_master_rxBuff[I2C_DATA_LENGTH];
+
+i2c_master_handle_t g_m_handle;
+
+volatile bool g_MasterCompletionFlag = false;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static void i2c_master_callback(I2C_Type *base, i2c_master_handle_t *handle, status_t status, void *userData)
+{
+    /* Signal transfer success when received success status. */
+    if (status == kStatus_Success)
+    {
+        g_MasterCompletionFlag = true;
+    }
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+    i2c_master_transfer_t masterXfer = {0};
+    status_t reVal                   = kStatus_Fail;
+
+    /* set BOD VBAT level to 1.65V */
+    POWER_SetBodVbatLevel(kPOWER_BodVbatLevel1650mv, kPOWER_BodHystLevel50mv, false);
+    /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
+    CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+
+    /* attach 12 MHz clock to FLEXCOMM8 (I2C master) */
+    CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
+
+    /* reset FLEXCOMM for I2C */
+    RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn);
+
+    BOARD_InitBootPins();
+    BOARD_InitBootClocks();
+    BOARD_InitDebugConsole();
+
+    PRINTF("\r\nI2C board2board interrupt example -- Master transfer.\r\n");
+
+    /* Set up i2c master to send data to slave*/
+    /* First data in txBuff is data length of the transmiting data. */
+    g_master_txBuff[0] = I2C_DATA_LENGTH - 1U;
+    for (uint32_t i = 1U; i < I2C_DATA_LENGTH; i++)
+    {
+        g_master_txBuff[i] = i - 1;
+    }
+
+    PRINTF("Master will send data :");
+    for (uint32_t i = 0U; i < I2C_DATA_LENGTH - 1U; i++)
+    {
+        if (i % 8 == 0)
+        {
+            PRINTF("\r\n");
+        }
+        PRINTF("0x%2x  ", g_master_txBuff[i + 1]);
+    }
+    PRINTF("\r\n\r\n");
+
+    i2c_master_config_t masterConfig;
+
+    /*
+     * masterConfig.debugEnable = false;
+     * masterConfig.ignoreAck = false;
+     * masterConfig.pinConfig = kI2C_2PinOpenDrain;
+     * masterConfig.baudRate_Bps = 100000U;
+     * masterConfig.busIdleTimeout_ns = 0;
+     * masterConfig.pinLowTimeout_ns = 0;
+     * masterConfig.sdaGlitchFilterWidth_ns = 0;
+     * masterConfig.sclGlitchFilterWidth_ns = 0;
+     */
+    I2C_MasterGetDefaultConfig(&masterConfig);
+
+    /* Change the default baudrate configuration */
+    masterConfig.baudRate_Bps = I2C_BAUDRATE;
+
+    /* Initialize the I2C master peripheral */
+    I2C_MasterInit(EXAMPLE_I2C_MASTER, &masterConfig, I2C_MASTER_CLOCK_FREQUENCY);
+
+    /* Create the I2C handle for the non-blocking transfer */
+    I2C_MasterTransferCreateHandle(EXAMPLE_I2C_MASTER, &g_m_handle, i2c_master_callback, NULL);
+
+    /* subAddress = 0x01, data = g_master_txBuff - write to slave.
+      start + slaveaddress(w) + subAddress + length of data buffer + data buffer + stop*/
+    uint8_t deviceAddress     = 0x01U;
+    masterXfer.slaveAddress   = I2C_MASTER_SLAVE_ADDR_7BIT;
+    masterXfer.direction      = kI2C_Write;
+    masterXfer.subaddress     = (uint32_t)deviceAddress;
+    masterXfer.subaddressSize = 1;
+    masterXfer.data           = g_master_txBuff;
+    masterXfer.dataSize       = I2C_DATA_LENGTH;
+    masterXfer.flags          = kI2C_TransferDefaultFlag;
+
+    /* Send master non-blocking data to slave */
+    reVal = I2C_MasterTransferNonBlocking(EXAMPLE_I2C_MASTER, &g_m_handle, &masterXfer);
+
+    /*  Reset master completion flag to false. */
+    g_MasterCompletionFlag = false;
+
+    if (reVal != kStatus_Success)
+    {
+        return -1;
+    }
+
+    /*  Wait for transfer completed. */
+    while (!g_MasterCompletionFlag)
+    {
+    }
+    g_MasterCompletionFlag = false;
+
+    PRINTF("Receive sent data from slave :");
+
+    /* subAddress = 0x01, data = g_master_rxBuff - read from slave.
+      start + slaveaddress(w) + subAddress + repeated start + slaveaddress(r) + rx data buffer + stop */
+    masterXfer.slaveAddress   = I2C_MASTER_SLAVE_ADDR_7BIT;
+    masterXfer.direction      = kI2C_Read;
+    masterXfer.subaddress     = (uint32_t)deviceAddress;
+    masterXfer.subaddressSize = 1;
+    masterXfer.data           = g_master_rxBuff;
+    masterXfer.dataSize       = I2C_DATA_LENGTH - 1;
+    masterXfer.flags          = kI2C_TransferDefaultFlag;
+
+    reVal = I2C_MasterTransferNonBlocking(EXAMPLE_I2C_MASTER, &g_m_handle, &masterXfer);
+
+    /*  Reset master completion flag to false. */
+    g_MasterCompletionFlag = false;
+
+    if (reVal != kStatus_Success)
+    {
+        return -1;
+    }
+
+    /*  Wait for transfer completed. */
+    while (!g_MasterCompletionFlag)
+    {
+    }
+    g_MasterCompletionFlag = false;
+
+    for (uint32_t i = 0U; i < I2C_DATA_LENGTH - 1; i++)
+    {
+        if (i % 8 == 0)
+        {
+            PRINTF("\r\n");
+        }
+        PRINTF("0x%2x  ", g_master_rxBuff[i]);
+    }
+    PRINTF("\r\n\r\n");
+
+    /* Transfer completed. Check the data.*/
+    for (uint32_t i = 0U; i < I2C_DATA_LENGTH - 1; i++)
+    {
+        if (g_master_rxBuff[i] != g_master_txBuff[i + 1])
+        {
+            PRINTF("\r\nError occurred in the transfer ! \r\n");
+            break;
+        }
+    }
+
+    PRINTF("\r\nEnd of I2C example .\r\n");
+    while (1)
+    {
+    }
+}

example_code/i2c/interrupt_b2b_transfer/master/i2c_interrupt_b2b_transfer_master_v3_9.xml

@@ -0,0 +1,124 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<ksdk:examples xmlns:ksdk="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd manifest.xsd">
+  <externalDefinitions>
+    <definition extID="utility.debug_console_lite.LPC55S16"/>
+    <definition extID="platform.utilities.assert_lite.LPC55S16"/>
+    <definition extID="platform.drivers.flexcomm_i2c.LPC55S16"/>
+    <definition extID="platform.drivers.common.LPC55S16"/>
+    <definition extID="platform.drivers.power.LPC55S16"/>
+    <definition extID="platform.drivers.lpc_iocon.LPC55S16"/>
+    <definition extID="platform.drivers.lpc_gpio.LPC55S16"/>
+    <definition extID="platform.drivers.inputmux.LPC55S16"/>
+    <definition extID="platform.drivers.clock.LPC55S16"/>
+    <definition extID="device.LPC55S16_CMSIS.LPC55S16"/>
+    <definition extID="device.LPC55S16_startup.LPC55S16"/>
+    <definition extID="platform.drivers.flexcomm_usart.LPC55S16"/>
+    <definition extID="platform.drivers.flexcomm.LPC55S16"/>
+    <definition extID="component.usart_adapter.LPC55S16"/>
+    <definition extID="component.lists.LPC55S16"/>
+    <definition extID="platform.drivers.reset.LPC55S16"/>
+    <definition extID="CMSIS_Include_core_cm.LPC55S16"/>
+    <definition extID="platform.drivers.inputmux_connections.LPC55S16"/>
+    <definition extID="platform.utilities.misc_utilities.LPC55S16"/>
+    <definition extID="device.LPC55S16_system.LPC55S16"/>
+    <definition extID="iar"/>
+    <definition extID="mdk"/>
+    <definition extID="armgcc"/>
+    <definition extID="mcuxpresso"/>
+    <definition extID="com.nxp.mcuxpresso"/>
+  </externalDefinitions>
+  <example id="lpcxpresso55s16_i2c_interrupt_b2b_transfer_master" name="i2c_interrupt_b2b_transfer_master" dependency="utility.debug_console_lite.LPC55S16 platform.utilities.assert_lite.LPC55S16 platform.drivers.flexcomm_i2c.LPC55S16 platform.drivers.common.LPC55S16 platform.drivers.power.LPC55S16 platform.drivers.lpc_iocon.LPC55S16 platform.drivers.lpc_gpio.LPC55S16 platform.drivers.inputmux.LPC55S16 platform.drivers.clock.LPC55S16 device.LPC55S16_CMSIS.LPC55S16 device.LPC55S16_startup.LPC55S16 platform.drivers.flexcomm_usart.LPC55S16 platform.drivers.flexcomm.LPC55S16 component.usart_adapter.LPC55S16 component.lists.LPC55S16 platform.drivers.reset.LPC55S16 CMSIS_Include_core_cm.LPC55S16 platform.drivers.inputmux_connections.LPC55S16 platform.utilities.misc_utilities.LPC55S16 device.LPC55S16_system.LPC55S16" category="driver_examples/i2c">
+    <projects>
+      <project type="com.crt.advproject.projecttype.exe" nature="org.eclipse.cdt.core.cnature"/>
+    </projects>
+    <toolchainSettings>
+      <toolchainSetting id_refs="com.nxp.mcuxpresso">
+        <option id="gnu.c.compiler.option.preprocessor.def.symbols" type="stringList">
+          <value>CPU_LPC55S16JBD100</value>
+          <value>MCUXPRESSO_SDK</value>
+        </option>
+        <option id="com.crt.advproject.gas.fpu" type="enum">
+          <value>com.crt.advproject.gas.fpu.fpv5sp.hard</value>
+        </option>
+        <option id="com.crt.advproject.gcc.fpu" type="enum">
+          <value>com.crt.advproject.gcc.fpu.fpv5sp.hard</value>
+        </option>
+        <option id="gnu.c.compiler.option.optimization.flags" type="string">
+          <value>-fno-common</value>
+        </option>
+        <option id="com.crt.advproject.c.misc.dialect" type="enum">
+          <value>com.crt.advproject.misc.dialect.gnu99</value>
+        </option>
+        <option id="gnu.c.compiler.option.misc.other" type="string">
+          <value>-mcpu=cortex-m33 -c -ffunction-sections -fdata-sections -ffreestanding -fno-builtin</value>
+        </option>
+        <option id="gnu.c.compiler.option.warnings.allwarn" type="boolean">
+          <value>false</value>
+        </option>
+        <option id="com.crt.advproject.link.fpu" type="enum">
+          <value>com.crt.advproject.link.fpu.fpv5sp.hard</value>
+        </option>
+        <option id="gnu.c.link.option.nostdlibs" type="boolean">
+          <value>true</value>
+        </option>
+      </toolchainSetting>
+    </toolchainSettings>
+    <include_paths>
+      <include_path path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/master" project_relative_path="board" type="c_include"/>
+    </include_paths>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/master/iar" project_relative_path="./" type="workspace" toolchain="iar">
+      <files mask="i2c_interrupt_b2b_transfer_master.ewd"/>
+      <files mask="i2c_interrupt_b2b_transfer_master.ewp"/>
+      <files mask="i2c_interrupt_b2b_transfer_master.eww"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/master/mdk" project_relative_path="./" type="workspace" toolchain="mdk">
+      <files mask="i2c_interrupt_b2b_transfer_master.uvprojx"/>
+      <files mask="i2c_interrupt_b2b_transfer_master.uvoptx"/>
+      <files mask="JLinkSettings.JLinkScript"/>
+      <files mask="JLinkSettings.ini"/>
+      <files mask="i2c_interrupt_b2b_transfer_master.uvmpw"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc" project_relative_path="./" type="workspace" toolchain="armgcc">
+      <files mask="build_all.bat"/>
+      <files mask="build_all.sh"/>
+      <files mask="clean.bat"/>
+      <files mask="clean.sh"/>
+      <files mask="CMakeLists.txt"/>
+      <files mask="flags.cmake"/>
+      <files mask="config.cmake"/>
+      <files mask="build_debug.bat"/>
+      <files mask="build_debug.sh"/>
+      <files mask="build_release.bat"/>
+      <files mask="build_release.sh"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/master" project_relative_path="source" type="src">
+      <files mask="i2c_interrupt_b2b_transfer_master.c"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/master" project_relative_path="board" type="src">
+      <files mask="pin_mux.c"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/master" project_relative_path="board" type="c_include">
+      <files mask="pin_mux.h"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/master" project_relative_path="board" type="src">
+      <files mask="board.c"/>
+      <files mask="clock_config.c"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/master" project_relative_path="board" type="c_include">
+      <files mask="board.h"/>
+      <files mask="clock_config.h"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/master" project_relative_path="doc" type="doc" toolchain="iar mdk mcuxpresso armgcc">
+      <files mask="readme.txt"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/master/iar" project_relative_path="LPC55S16/iar" type="linker" toolchain="iar">
+      <files mask="LPC55S16_flash.icf"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/master/mdk" project_relative_path="LPC55S16/arm" type="linker" toolchain="mdk">
+      <files mask="LPC55S16_flash.scf"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc" project_relative_path="LPC55S16/gcc" type="linker" toolchain="armgcc">
+      <files mask="LPC55S16_flash.ld"/>
+    </source>
+  </example>
+</ksdk:examples>

example_code/i2c/interrupt_b2b_transfer/master/pin_mux.c

@@ -0,0 +1,133 @@
+/*
+ * Copyright 2017-2020 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: LPC55S16
+package_id: LPC55S16JBD100
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_iocon.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29,
+    mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: inactive, slew_rate: standard,
+    invert: disabled, open_drain: disabled}
+  - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: inactive,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 */
+void BOARD_InitPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    const uint32_t port0_pin29_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
+                                         IOCON_PIO_FUNC1 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, 0U, 29U, port0_pin29_config);
+
+    const uint32_t port0_pin30_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
+                                         IOCON_PIO_FUNC1 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, 0U, 30U, port0_pin30_config);
+
+    const uint32_t port1_pin20_config = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */
+                                         IOCON_PIO_FUNC5 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, 1U, 20U, port1_pin20_config);
+
+    const uint32_t port1_pin21_config = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */
+                                         IOCON_PIO_FUNC5 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, 1U, 21U, port1_pin21_config);
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/

example_code/i2c/interrupt_b2b_transfer/master/pin_mux.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright 2017-2020 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC1 0x01u         /*!<@brief Selects pin function 1 */
+#define IOCON_PIO_FUNC5 0x05u         /*!<@brief Selects pin function 5 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u    /*!<@brief No addition pin function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/

example_code/i2c/interrupt_b2b_transfer/master/readme.txt

@@ -0,0 +1,70 @@
+Overview
+========
+The i2c_interrupt_b2b_transfer_master example shows how to use i2c driver as master to do board to board transfer 
+with interrupt:
+
+In this example, one i2c instance as master and another i2c instance on the other board as slave. Master sends a 
+piece of data to slave, and receive a piece of data from slave. This example checks if the data received from 
+slave is correct.
+
+
+Toolchain supported
+===================
+- IAR embedded Workbench  9.10.2
+- Keil MDK  5.34
+- GCC ARM Embedded  10.2.1
+- MCUXpresso  11.5.0
+
+Hardware requirements
+=====================
+- Micro USB cable
+- Two LPCXpresso55S16 boards
+- Personal Computer
+
+Board settings
+==============
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+MASTER_BOARD        CONNECTS TO         SLAVE_BOARD
+Pin Name   Board Location     Pin Name   Board Location
+I2C_SCL    J9-2               I2C_SCL    J9-2
+I2C_SDA    J9-4               I2C_SDA    J9-4
+GND        J9-8               GND        J9-8 
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The jumper setting:
+    Default jumpers configuration does not work,  you will need to add JP20 and JP21 (JP22 optional for ADC use)
+    
+Prepare the Demo
+================
+1. Connect a micro USB cable between the PC host and the LPC-Link USB port (J1) on the board.
+2. Open a serial terminal on PC for JLink serial device with these settings:
+   - 115200 baud rate
+   - 8 data bits
+   - No parity
+   - One stop bit
+   - No flow control
+3. Download the program to the target board.
+4. Either press the reset button on your board or launch the debugger in your IDE to begin running
+   the demo.
+
+Running the demo
+================
+The following message shows in the terminal if the example runs successfully.
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+I2C board2board interrupt example -- Master transfer.
+Master will send data :
+0x 0  0x 1  0x 2  0x 3  0x 4  0x 5  0x 6  0x 7
+0x 8  0x 9  0x a  0x b  0x c  0x d  0x e  0x f
+0x10  0x11  0x12  0x13  0x14  0x15  0x16  0x17
+0x18  0x19  0x1a  0x1b  0x1c  0x1d  0x1e  0x1f
+
+Receive sent data from slave :
+0x 0  0x 1  0x 2  0x 3  0x 4  0x 5  0x 6  0x 7
+0x 8  0x 9  0x a  0x b  0x c  0x d  0x e  0x f
+0x10  0x11  0x12  0x13  0x14  0x15  0x16  0x17
+0x18  0x19  0x1a  0x1b  0x1c  0x1d  0x1e  0x1f
+
+
+End of I2C example .
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~

example_code/i2c/interrupt_b2b_transfer/slave/board.c

@@ -0,0 +1,122 @@
+/*
+ * Copyright 2017-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "board.h"
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+#include "fsl_i2c.h"
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+    /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
+    CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+
+    RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST);
+
+    uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+
+    DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz)
+{
+    i2c_master_config_t i2cConfig = {0};
+
+    I2C_MasterGetDefaultConfig(&i2cConfig);
+    I2C_MasterInit(base, &i2cConfig, clkSrc_Hz);
+}
+
+status_t BOARD_I2C_Send(I2C_Type *base,
+                        uint8_t deviceAddress,
+                        uint32_t subAddress,
+                        uint8_t subaddressSize,
+                        uint8_t *txBuff,
+                        uint8_t txBuffSize)
+{
+    i2c_master_transfer_t masterXfer;
+
+    /* Prepare transfer structure. */
+    masterXfer.slaveAddress   = deviceAddress;
+    masterXfer.direction      = kI2C_Write;
+    masterXfer.subaddress     = subAddress;
+    masterXfer.subaddressSize = subaddressSize;
+    masterXfer.data           = txBuff;
+    masterXfer.dataSize       = txBuffSize;
+    masterXfer.flags          = kI2C_TransferDefaultFlag;
+
+    return I2C_MasterTransferBlocking(base, &masterXfer);
+}
+
+status_t BOARD_I2C_Receive(I2C_Type *base,
+                           uint8_t deviceAddress,
+                           uint32_t subAddress,
+                           uint8_t subaddressSize,
+                           uint8_t *rxBuff,
+                           uint8_t rxBuffSize)
+{
+    i2c_master_transfer_t masterXfer;
+
+    /* Prepare transfer structure. */
+    masterXfer.slaveAddress   = deviceAddress;
+    masterXfer.subaddress     = subAddress;
+    masterXfer.subaddressSize = subaddressSize;
+    masterXfer.data           = rxBuff;
+    masterXfer.dataSize       = rxBuffSize;
+    masterXfer.direction      = kI2C_Read;
+    masterXfer.flags          = kI2C_TransferDefaultFlag;
+
+    return I2C_MasterTransferBlocking(base, &masterXfer);
+}
+
+void BOARD_Accel_I2C_Init(void)
+{
+    BOARD_I2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
+{
+    uint8_t data = (uint8_t)txBuff;
+
+    return BOARD_I2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
+}
+
+status_t BOARD_Accel_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+    return BOARD_I2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
+}
+
+void BOARD_Codec_I2C_Init(void)
+{
+    BOARD_I2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Codec_I2C_Send(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
+{
+    return BOARD_I2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
+                          txBuffSize);
+}
+
+status_t BOARD_Codec_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+    return BOARD_I2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
+}
+#endif /* SDK_I2C_BASED_COMPONENT_USED */

example_code/i2c/interrupt_b2b_transfer/slave/board.h

@@ -0,0 +1,230 @@
+/*
+ * Copyright 2017-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "clock_config.h"
+#include "fsl_common.h"
+#include "fsl_reset.h"
+#include "fsl_gpio.h"
+#include "fsl_iocon.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "LPCXpresso55S16"
+
+/*! @brief The UART to use for debug messages. */
+/* TODO: rename UART to USART */
+#define BOARD_DEBUG_UART_TYPE       kSerialPort_Uart
+#define BOARD_DEBUG_UART_BASEADDR   (uint32_t) USART0
+#define BOARD_DEBUG_UART_INSTANCE   0U
+#define BOARD_DEBUG_UART_CLK_FREQ   12000000U
+#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM0
+#define BOARD_DEBUG_UART_RST        kFC0_RST_SHIFT_RSTn
+#define BOARD_DEBUG_UART_CLKSRC     kCLOCK_Flexcomm0
+#define BOARD_UART_IRQ_HANDLER      FLEXCOMM0_IRQHandler
+#define BOARD_UART_IRQ              FLEXCOMM0_IRQn
+
+#define BOARD_ACCEL_I2C_BASEADDR   I2C4
+#define BOARD_ACCEL_I2C_CLOCK_FREQ 12000000
+
+#ifndef BOARD_DEBUG_UART_BAUDRATE
+#define BOARD_DEBUG_UART_BAUDRATE 115200U
+#endif /* BOARD_DEBUG_UART_BAUDRATE */
+
+#define BOARD_CODEC_I2C_BASEADDR   I2C4
+#define BOARD_CODEC_I2C_CLOCK_FREQ 12000000
+#define BOARD_CODEC_I2C_INSTANCE   4
+#ifndef BOARD_LED_RED_GPIO
+#define BOARD_LED_RED_GPIO GPIO
+#endif
+#define BOARD_LED_RED_GPIO_PORT 1U
+#ifndef BOARD_LED_RED_GPIO_PIN
+#define BOARD_LED_RED_GPIO_PIN 4U
+#endif
+
+#ifndef BOARD_LED_BLUE_GPIO
+#define BOARD_LED_BLUE_GPIO GPIO
+#endif
+#define BOARD_LED_BLUE_GPIO_PORT 1U
+#ifndef BOARD_LED_BLUE_GPIO_PIN
+#define BOARD_LED_BLUE_GPIO_PIN 6U
+#endif
+
+#ifndef BOARD_LED_GREEN_GPIO
+#define BOARD_LED_GREEN_GPIO GPIO
+#endif
+#define BOARD_LED_GREEN_GPIO_PORT 1U
+#ifndef BOARD_LED_GREEN_GPIO_PIN
+#define BOARD_LED_GREEN_GPIO_PIN 7U
+#endif
+
+#ifndef BOARD_SW1_GPIO
+#define BOARD_SW1_GPIO GPIO
+#endif
+#define BOARD_SW1_GPIO_PORT 1U
+#ifndef BOARD_SW1_GPIO_PIN
+#define BOARD_SW1_GPIO_PIN 18U
+#endif
+#define BOARD_SW1_NAME        "SW1"
+#define BOARD_SW1_IRQ         PIN_INT1_IRQn
+#define BOARD_SW1_IRQ_HANDLER PIN_INT1_IRQHandler
+
+#ifndef BOARD_SW3_GPIO
+#define BOARD_SW3_GPIO GPIO
+#endif
+#define BOARD_SW3_GPIO_PORT 1U
+#ifndef BOARD_SW3_GPIO_PIN
+#define BOARD_SW3_GPIO_PIN 9U
+#endif
+#define BOARD_SW3_NAME              "SW3"
+#define BOARD_SW3_IRQ               PIN_INT1_IRQn
+#define BOARD_SW3_IRQ_HANDLER       PIN_INT1_IRQHandler
+#define BOARD_SW3_GPIO_PININT_INDEX 1
+
+#ifndef BOARD_SW4_GPIO
+#define BOARD_SW4_GPIO GPIO
+#endif
+#define BOARD_SW4_GPIO_PORT 0U
+#ifndef BOARD_SW4_GPIO_PIN
+#define BOARD_SW4_GPIO_PIN 5U
+#endif
+#define BOARD_SW4_NAME              "SW4"
+#define BOARD_SW4_IRQ               PIN_INT0_IRQn
+#define BOARD_SW4_IRQ_HANDLER       PIN_INT0_IRQHandler
+#define BOARD_SW4_GPIO_PININT_INDEX 1
+
+/* USB PHY condfiguration */
+#define BOARD_USB_PHY_D_CAL     (0x05U)
+#define BOARD_USB_PHY_TXCAL45DP (0x0AU)
+#define BOARD_USB_PHY_TXCAL45DM (0x0AU)
+
+#define BOARD_SDIF_BASEADDR       SDIF
+#define BOARD_SDIF_CLKSRC         kCLOCK_SDio
+#define BOARD_SDIF_CLK_FREQ       CLOCK_GetSdioClkFreq()
+#define BOARD_SDIF_CLK_ATTACH     kMAIN_CLK_to_SDIO_CLK
+#define BOARD_SDIF_IRQ            SDIO_IRQn
+#define BOARD_MMC_VCC_SUPPLY      kMMC_VoltageWindows270to360
+#define BOARD_SD_CARD_DETECT_PIN  17
+#define BOARD_SD_CARD_DETECT_PORT 0
+#define BOARD_SD_CARD_DETECT_GPIO GPIO
+#define BOARD_SD_DETECT_TYPE      kSDMMCHOST_DetectCardByHostCD
+
+#define BOARD_SDIF_CD_GPIO_INIT()                                                                    \
+    {                                                                                                \
+        CLOCK_EnableClock(kCLOCK_Gpio2);                                                             \
+        GPIO_PinInit(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN, \
+                     &(gpio_pin_config_t){kGPIO_DigitalInput, 0U});                                  \
+    }
+#define BOARD_SDIF_CD_STATUS() \
+    GPIO_PinRead(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN)
+
+/* Board led color mapping */
+#define LOGIC_LED_ON  1U
+#define LOGIC_LED_OFF 0U
+
+#define BOARD_SDIF_CLK_ATTACH kMAIN_CLK_to_SDIO_CLK
+
+#define LED_RED_INIT(output)                                                                          \
+    {                                                                                                 \
+        IOCON_PinMuxSet(IOCON, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, IOCON_DIGITAL_EN);    \
+        GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN,             \
+                     &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \
+    }
+#define LED_RED_OFF()                                           \
+    GPIO_PortClear(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+                   1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED1 */
+#define LED_RED_ON()                                                                        \
+    GPIO_PortSet(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT,                               \
+                 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED1 \ \ \ \ \ \ \ \ \ \ \
+                                                */
+#define LED_RED_TOGGLE()                                         \
+    GPIO_PortToggle(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+                    1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED1 */
+
+#define LED_BLUE_INIT(output)                                                                         \
+    {                                                                                                 \
+        IOCON_PinMuxSet(IOCON, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, IOCON_DIGITAL_EN);  \
+        GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN,          \
+                     &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \
+    }
+#define LED_BLUE_OFF()                                            \
+    GPIO_PortClear(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                   1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED1 */
+#define LED_BLUE_ON()                                           \
+    GPIO_PortSet(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED1 */
+#define LED_BLUE_TOGGLE()                                          \
+    GPIO_PortToggle(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                    1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED1 */
+
+#define LED_GREEN_INIT(output)                                                              \
+    GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, BOARD_LED_GREEN_GPIO_PIN, \
+                 &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED1 */
+#define LED_GREEN_OFF()                                             \
+    GPIO_PortClear(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                   1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED1 */
+#define LED_GREEN_ON()                                            \
+    GPIO_PortSet(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED1 */
+#define LED_GREEN_TOGGLE()                                           \
+    GPIO_PortToggle(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                    1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED1 */
+
+/* Display. */
+#define BOARD_LCD_DC_GPIO      GPIO
+#define BOARD_LCD_DC_GPIO_PORT 1U
+#define BOARD_LCD_DC_GPIO_PIN  5U
+
+/* Serial MWM WIFI */
+#define BOARD_SERIAL_MWM_PORT_CLK_FREQ CLOCK_GetFlexCommClkFreq(2)
+#define BOARD_SERIAL_MWM_PORT          USART2
+#define BOARD_SERIAL_MWM_PORT_IRQn     FLEXCOMM2_IRQn
+#define BOARD_SERIAL_MWM_RST_WRITE(output)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz);
+status_t BOARD_I2C_Send(I2C_Type *base,
+                        uint8_t deviceAddress,
+                        uint32_t subAddress,
+                        uint8_t subaddressSize,
+                        uint8_t *txBuff,
+                        uint8_t txBuffSize);
+status_t BOARD_I2C_Receive(I2C_Type *base,
+                           uint8_t deviceAddress,
+                           uint32_t subAddress,
+                           uint8_t subaddressSize,
+                           uint8_t *rxBuff,
+                           uint8_t rxBuffSize);
+void BOARD_Accel_I2C_Init(void);
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
+status_t BOARD_Accel_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+void BOARD_Codec_I2C_Init(void);
+status_t BOARD_Codec_I2C_Send(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
+status_t BOARD_Codec_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */

example_code/i2c/interrupt_b2b_transfer/slave/clock_config.c

@@ -0,0 +1,380 @@
+/*
+ * Copyright 2017-2018 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to set up clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up wait states of the flash.
+ *
+ * 3. Set up all dividers.
+ *
+ * 4. Set up all selectors to provide selected clocks.
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v7.0
+processor: LPC55S16
+package_id: LPC55S16JBD100
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+board: LPCXpresso55S16
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockPLL150M();
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 12 MHz}
+settings:
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    POWER_SetVoltageForFreq(12000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(12000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO12M */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF96M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF96M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    POWER_SetVoltageForFreq(96000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(96000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL100M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 100 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
+- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
+- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL100M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable High speed Crystal oscillator output to system  */
+
+    POWER_SetVoltageForFreq(100000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(100000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U),
+        .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
+        .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
+        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+        .pllRate = 100000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL150M
+called_from_default_init: true
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 150 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true}
+- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true}
+- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true}
+sources:
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL150M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable High speed Crystal oscillator output to system  */
+
+    POWER_SetVoltageForFreq(150000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(150000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
+        .pllndec = SYSCON_PLL0NDEC_NDIV(8U),
+        .pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
+        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+        .pllRate = 150000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockPLL1_150M ********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL1_150M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 150 MHz}
+settings:
+- {id: PLL1_Mode, value: Normal}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS}
+- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL1M_MULT.scale, value: '150', locked: true}
+- {id: SYSCON.PLL1N_DIV.scale, value: '8', locked: true}
+- {id: SYSCON.PLL1_PDEC.scale, value: '2', locked: true}
+sources:
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL1_150M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable High speed Crystal oscillator output to system  */
+
+    POWER_SetVoltageForFreq(150000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(150000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL1 */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL1);                    /*!< Switch PLL1CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL1);                  /* Ensure PLL is on  */
+    const pll_setup_t pll1Setup = {
+        .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(53U) | SYSCON_PLL1CTRL_SELP(31U),
+        .pllndec = SYSCON_PLL1NDEC_NDIV(8U),
+        .pllpdec = SYSCON_PLL1PDEC_PDIV(1U),
+        .pllmdec = SYSCON_PLL1MDEC_MDIV(150U),
+        .pllRate = 150000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL1Freq(&pll1Setup);                        /*!< Configure PLL1 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL1_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL1 */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK;
+#endif
+}
+

example_code/i2c/interrupt_b2b_transfer/slave/clock_config.h

@@ -0,0 +1,173 @@
+/*
+ * Copyright 2017-2018 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         16000000U  /*!< Board xtal frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK         96000000U  /*!< Core clock frequency: 96000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF96M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL100M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         150000000U  /*!< Core clock frequency: 150000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockPLL1_150M ********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK       150000000U  /*!< Core clock frequency: 150000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL1_150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+

example_code/i2c/interrupt_b2b_transfer/slave/i2c_interrupt_b2b_transfer_slave.c

@@ -0,0 +1,151 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*  Standard C Included Files */
+#include <stdio.h>
+#include <string.h>
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_debug_console.h"
+#include "fsl_i2c.h"
+
+#include "fsl_power.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define EXAMPLE_I2C_SLAVE_BASE    (I2C4_BASE)
+#define I2C_SLAVE_CLOCK_FREQUENCY (12000000)
+#define EXAMPLE_I2C_SLAVE ((I2C_Type *)EXAMPLE_I2C_SLAVE_BASE)
+
+#define I2C_MASTER_SLAVE_ADDR_7BIT (0x7EU)
+#define I2C_DATA_LENGTH            (34) /* MAX is 256 */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+uint8_t g_slave_buff[I2C_DATA_LENGTH];
+i2c_slave_handle_t g_s_handle;
+volatile bool g_SlaveCompletionFlag = false;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static void i2c_slave_callback(I2C_Type *base, volatile i2c_slave_transfer_t *xfer, void *userData)
+{
+    switch (xfer->event)
+    {
+        /*  Address match event */
+        case kI2C_SlaveAddressMatchEvent:
+            xfer->rxData = NULL;
+            xfer->rxSize = 0;
+            break;
+        /*  Transmit request */
+        case kI2C_SlaveTransmitEvent:
+            /*  Update information for transmit process */
+            xfer->txData = &g_slave_buff[2];
+            xfer->txSize = g_slave_buff[1];
+            break;
+
+        /* Setup the slave receive buffer */
+        case kI2C_SlaveReceiveEvent:
+            /*  Update information for received process */
+            xfer->rxData = g_slave_buff;
+            xfer->rxSize = I2C_DATA_LENGTH;
+            break;
+
+        /* The master has sent a stop transition on the bus */
+        case kI2C_SlaveCompletionEvent:
+            g_SlaveCompletionFlag = true;
+            break;
+
+        default:
+            g_SlaveCompletionFlag = false;
+            break;
+    }
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+    i2c_slave_config_t slaveConfig;
+    status_t reVal = kStatus_Fail;
+
+    /* set BOD VBAT level to 1.65V */
+    POWER_SetBodVbatLevel(kPOWER_BodVbatLevel1650mv, kPOWER_BodHystLevel50mv, false);
+    /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
+    CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+
+    /* attach 12 MHz clock to FLEXCOMM8 (I2C master) */
+    CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
+
+    /* reset FLEXCOMM for I2C */
+    RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn);
+
+    BOARD_InitBootPins();
+    BOARD_InitBootClocks();
+    BOARD_InitDebugConsole();
+
+    PRINTF("\r\nI2C board2board interrupt example -- Slave transfer.\r\n\r\n");
+
+    /* Set up i2c slave */
+    I2C_SlaveGetDefaultConfig(&slaveConfig);
+
+    /* Change the slave address */
+    slaveConfig.address0.address = I2C_MASTER_SLAVE_ADDR_7BIT;
+
+    /* Initialize the I2C slave peripheral */
+    I2C_SlaveInit(EXAMPLE_I2C_SLAVE, &slaveConfig, I2C_SLAVE_CLOCK_FREQUENCY);
+
+    memset(g_slave_buff, 0, sizeof(g_slave_buff));
+
+    /* Create the I2C handle for the non-blocking transfer */
+    I2C_SlaveTransferCreateHandle(EXAMPLE_I2C_SLAVE, &g_s_handle, i2c_slave_callback, NULL);
+
+    /* Start accepting I2C transfers on the I2C slave peripheral */
+    reVal = I2C_SlaveTransferNonBlocking(EXAMPLE_I2C_SLAVE, &g_s_handle,
+                                         kI2C_SlaveAddressMatchEvent | kI2C_SlaveCompletionEvent);
+    if (reVal != kStatus_Success)
+    {
+        return -1;
+    }
+
+    /*  Wait for transfer completed. */
+    while (!g_SlaveCompletionFlag)
+    {
+    }
+    g_SlaveCompletionFlag = false;
+
+    PRINTF("Slave received data :");
+    for (uint32_t i = 0U; i < g_slave_buff[1]; i++)
+    {
+        if (i % 8 == 0)
+        {
+            PRINTF("\r\n");
+        }
+        PRINTF("0x%2x  ", g_slave_buff[2 + i]);
+    }
+    PRINTF("\r\n\r\n");
+
+    /* Wait for master receive completed.*/
+    while (!g_SlaveCompletionFlag)
+    {
+    }
+    g_SlaveCompletionFlag = false;
+
+    PRINTF("\r\nEnd of I2C example .\r\n");
+    while (1)
+    {
+    }
+}

example_code/i2c/interrupt_b2b_transfer/slave/i2c_interrupt_b2b_transfer_slave_v3_9.xml

@@ -0,0 +1,124 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<ksdk:examples xmlns:ksdk="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd manifest.xsd">
+  <externalDefinitions>
+    <definition extID="utility.debug_console_lite.LPC55S16"/>
+    <definition extID="platform.utilities.assert_lite.LPC55S16"/>
+    <definition extID="platform.drivers.flexcomm_i2c.LPC55S16"/>
+    <definition extID="platform.drivers.common.LPC55S16"/>
+    <definition extID="platform.drivers.power.LPC55S16"/>
+    <definition extID="platform.drivers.lpc_iocon.LPC55S16"/>
+    <definition extID="platform.drivers.lpc_gpio.LPC55S16"/>
+    <definition extID="platform.drivers.inputmux.LPC55S16"/>
+    <definition extID="platform.drivers.clock.LPC55S16"/>
+    <definition extID="device.LPC55S16_CMSIS.LPC55S16"/>
+    <definition extID="device.LPC55S16_startup.LPC55S16"/>
+    <definition extID="platform.drivers.flexcomm_usart.LPC55S16"/>
+    <definition extID="platform.drivers.flexcomm.LPC55S16"/>
+    <definition extID="component.usart_adapter.LPC55S16"/>
+    <definition extID="component.lists.LPC55S16"/>
+    <definition extID="platform.drivers.reset.LPC55S16"/>
+    <definition extID="CMSIS_Include_core_cm.LPC55S16"/>
+    <definition extID="platform.drivers.inputmux_connections.LPC55S16"/>
+    <definition extID="platform.utilities.misc_utilities.LPC55S16"/>
+    <definition extID="device.LPC55S16_system.LPC55S16"/>
+    <definition extID="iar"/>
+    <definition extID="mdk"/>
+    <definition extID="armgcc"/>
+    <definition extID="mcuxpresso"/>
+    <definition extID="com.nxp.mcuxpresso"/>
+  </externalDefinitions>
+  <example id="lpcxpresso55s16_i2c_interrupt_b2b_transfer_slave" name="i2c_interrupt_b2b_transfer_slave" dependency="utility.debug_console_lite.LPC55S16 platform.utilities.assert_lite.LPC55S16 platform.drivers.flexcomm_i2c.LPC55S16 platform.drivers.common.LPC55S16 platform.drivers.power.LPC55S16 platform.drivers.lpc_iocon.LPC55S16 platform.drivers.lpc_gpio.LPC55S16 platform.drivers.inputmux.LPC55S16 platform.drivers.clock.LPC55S16 device.LPC55S16_CMSIS.LPC55S16 device.LPC55S16_startup.LPC55S16 platform.drivers.flexcomm_usart.LPC55S16 platform.drivers.flexcomm.LPC55S16 component.usart_adapter.LPC55S16 component.lists.LPC55S16 platform.drivers.reset.LPC55S16 CMSIS_Include_core_cm.LPC55S16 platform.drivers.inputmux_connections.LPC55S16 platform.utilities.misc_utilities.LPC55S16 device.LPC55S16_system.LPC55S16" category="driver_examples/i2c">
+    <projects>
+      <project type="com.crt.advproject.projecttype.exe" nature="org.eclipse.cdt.core.cnature"/>
+    </projects>
+    <toolchainSettings>
+      <toolchainSetting id_refs="com.nxp.mcuxpresso">
+        <option id="gnu.c.compiler.option.preprocessor.def.symbols" type="stringList">
+          <value>CPU_LPC55S16JBD100</value>
+          <value>MCUXPRESSO_SDK</value>
+        </option>
+        <option id="com.crt.advproject.gas.fpu" type="enum">
+          <value>com.crt.advproject.gas.fpu.fpv5sp.hard</value>
+        </option>
+        <option id="com.crt.advproject.gcc.fpu" type="enum">
+          <value>com.crt.advproject.gcc.fpu.fpv5sp.hard</value>
+        </option>
+        <option id="gnu.c.compiler.option.optimization.flags" type="string">
+          <value>-fno-common</value>
+        </option>
+        <option id="com.crt.advproject.c.misc.dialect" type="enum">
+          <value>com.crt.advproject.misc.dialect.gnu99</value>
+        </option>
+        <option id="gnu.c.compiler.option.misc.other" type="string">
+          <value>-mcpu=cortex-m33 -c -ffunction-sections -fdata-sections -ffreestanding -fno-builtin</value>
+        </option>
+        <option id="gnu.c.compiler.option.warnings.allwarn" type="boolean">
+          <value>false</value>
+        </option>
+        <option id="com.crt.advproject.link.fpu" type="enum">
+          <value>com.crt.advproject.link.fpu.fpv5sp.hard</value>
+        </option>
+        <option id="gnu.c.link.option.nostdlibs" type="boolean">
+          <value>true</value>
+        </option>
+      </toolchainSetting>
+    </toolchainSettings>
+    <include_paths>
+      <include_path path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/slave" project_relative_path="board" type="c_include"/>
+    </include_paths>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/slave/iar" project_relative_path="./" type="workspace" toolchain="iar">
+      <files mask="i2c_interrupt_b2b_transfer_slave.ewd"/>
+      <files mask="i2c_interrupt_b2b_transfer_slave.ewp"/>
+      <files mask="i2c_interrupt_b2b_transfer_slave.eww"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/slave/mdk" project_relative_path="./" type="workspace" toolchain="mdk">
+      <files mask="i2c_interrupt_b2b_transfer_slave.uvprojx"/>
+      <files mask="i2c_interrupt_b2b_transfer_slave.uvoptx"/>
+      <files mask="JLinkSettings.JLinkScript"/>
+      <files mask="JLinkSettings.ini"/>
+      <files mask="i2c_interrupt_b2b_transfer_slave.uvmpw"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc" project_relative_path="./" type="workspace" toolchain="armgcc">
+      <files mask="build_all.bat"/>
+      <files mask="build_all.sh"/>
+      <files mask="clean.bat"/>
+      <files mask="clean.sh"/>
+      <files mask="CMakeLists.txt"/>
+      <files mask="flags.cmake"/>
+      <files mask="config.cmake"/>
+      <files mask="build_debug.bat"/>
+      <files mask="build_debug.sh"/>
+      <files mask="build_release.bat"/>
+      <files mask="build_release.sh"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/slave" project_relative_path="source" type="src">
+      <files mask="i2c_interrupt_b2b_transfer_slave.c"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/slave" project_relative_path="board" type="src">
+      <files mask="pin_mux.c"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/slave" project_relative_path="board" type="c_include">
+      <files mask="pin_mux.h"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/slave" project_relative_path="board" type="src">
+      <files mask="board.c"/>
+      <files mask="clock_config.c"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/slave" project_relative_path="board" type="c_include">
+      <files mask="board.h"/>
+      <files mask="clock_config.h"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/slave" project_relative_path="doc" type="doc" toolchain="iar mdk mcuxpresso armgcc">
+      <files mask="readme.txt"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/slave/iar" project_relative_path="LPC55S16/iar" type="linker" toolchain="iar">
+      <files mask="LPC55S16_flash.icf"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/slave/mdk" project_relative_path="LPC55S16/arm" type="linker" toolchain="mdk">
+      <files mask="LPC55S16_flash.scf"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc" project_relative_path="LPC55S16/gcc" type="linker" toolchain="armgcc">
+      <files mask="LPC55S16_flash.ld"/>
+    </source>
+  </example>
+</ksdk:examples>

example_code/i2c/interrupt_b2b_transfer/slave/pin_mux.c

@@ -0,0 +1,133 @@
+/*
+ * Copyright 2017-2020 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: LPC55S16
+package_id: LPC55S16JBD100
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_iocon.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29,
+    mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: inactive, slew_rate: standard,
+    invert: disabled, open_drain: disabled}
+  - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: inactive,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 */
+void BOARD_InitPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    const uint32_t port0_pin29_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
+                                         IOCON_PIO_FUNC1 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, 0U, 29U, port0_pin29_config);
+
+    const uint32_t port0_pin30_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
+                                         IOCON_PIO_FUNC1 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, 0U, 30U, port0_pin30_config);
+
+    const uint32_t port1_pin20_config = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */
+                                         IOCON_PIO_FUNC5 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, 1U, 20U, port1_pin20_config);
+
+    const uint32_t port1_pin21_config = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */
+                                         IOCON_PIO_FUNC5 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, 1U, 21U, port1_pin21_config);
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/

example_code/i2c/interrupt_b2b_transfer/slave/pin_mux.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright 2017-2020 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC1 0x01u         /*!<@brief Selects pin function 1 */
+#define IOCON_PIO_FUNC5 0x05u         /*!<@brief Selects pin function 5 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u    /*!<@brief No addition pin function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/

example_code/i2c/interrupt_b2b_transfer/slave/readme.txt

@@ -0,0 +1,64 @@
+Overview
+========
+The i2c_interrupt_b2b_transfer_slave example shows how to use i2c driver as slave to do board to board transfer 
+with interrupt:
+
+In this example, one i2c instance as slave and another i2c instance on the other board as master. Master sends a 
+piece of data to slave, and receive a piece of data from slave. This example checks if the data received from 
+slave is correct.
+
+Toolchain supported
+===================
+- IAR embedded Workbench  9.10.2
+- Keil MDK  5.34
+- GCC ARM Embedded  10.2.1
+- MCUXpresso  11.5.0
+
+Hardware requirements
+=====================
+- Micro USB cable
+- Two LPCXpresso55S16 boards
+- Personal Computer
+
+Board settings
+==============
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+MASTER_BOARD        CONNECTS TO         SLAVE_BOARD
+Pin Name   Board Location     Pin Name   Board Location
+I2C_SCL    J9-2               I2C_SCL    J9-2
+I2C_SDA    J9-4               I2C_SDA    J9-4
+GND        J9-8               GND        J9-8   
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The jumper setting:
+    Default jumpers configuration does not work,  you will need to add JP20 and JP21 (JP22 optional for ADC use)
+    
+Prepare the Demo
+================
+1. Connect a micro USB cable between the PC host and the LPC-Link USB port (J1) on the board.
+2. Open a serial terminal on PC for JLink serial device with these settings:
+   - 115200 baud rate
+   - 8 data bits
+   - No parity
+   - One stop bit
+   - No flow control
+3. Download the program to the target board.
+4. Either press the reset button on your board or launch the debugger in your IDE to begin running
+   the demo.
+
+Running the demo
+================
+The following message shows in the terminal if the example runs successfully.
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+I2C board2board interrupt example -- Slave transfer.
+
+Slave received data :
+0x 0  0x 1  0x 2  0x 3  0x 4  0x 5  0x 6  0x 7  
+0x 8  0x 9  0x a  0x b  0x c  0x d  0x e  0x f  
+0x10  0x11  0x12  0x13  0x14  0x15  0x16  0x17  
+0x18  0x19  0x1a  0x1b  0x1c  0x1d  0x1e  0x1f  
+
+
+End of I2C example .
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~

example_code/i2c/polling_b2b/master/board.c

@@ -0,0 +1,122 @@
+/*
+ * Copyright 2017-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "board.h"
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+#include "fsl_i2c.h"
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+    /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
+    CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+
+    RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST);
+
+    uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+
+    DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz)
+{
+    i2c_master_config_t i2cConfig = {0};
+
+    I2C_MasterGetDefaultConfig(&i2cConfig);
+    I2C_MasterInit(base, &i2cConfig, clkSrc_Hz);
+}
+
+status_t BOARD_I2C_Send(I2C_Type *base,
+                        uint8_t deviceAddress,
+                        uint32_t subAddress,
+                        uint8_t subaddressSize,
+                        uint8_t *txBuff,
+                        uint8_t txBuffSize)
+{
+    i2c_master_transfer_t masterXfer;
+
+    /* Prepare transfer structure. */
+    masterXfer.slaveAddress   = deviceAddress;
+    masterXfer.direction      = kI2C_Write;
+    masterXfer.subaddress     = subAddress;
+    masterXfer.subaddressSize = subaddressSize;
+    masterXfer.data           = txBuff;
+    masterXfer.dataSize       = txBuffSize;
+    masterXfer.flags          = kI2C_TransferDefaultFlag;
+
+    return I2C_MasterTransferBlocking(base, &masterXfer);
+}
+
+status_t BOARD_I2C_Receive(I2C_Type *base,
+                           uint8_t deviceAddress,
+                           uint32_t subAddress,
+                           uint8_t subaddressSize,
+                           uint8_t *rxBuff,
+                           uint8_t rxBuffSize)
+{
+    i2c_master_transfer_t masterXfer;
+
+    /* Prepare transfer structure. */
+    masterXfer.slaveAddress   = deviceAddress;
+    masterXfer.subaddress     = subAddress;
+    masterXfer.subaddressSize = subaddressSize;
+    masterXfer.data           = rxBuff;
+    masterXfer.dataSize       = rxBuffSize;
+    masterXfer.direction      = kI2C_Read;
+    masterXfer.flags          = kI2C_TransferDefaultFlag;
+
+    return I2C_MasterTransferBlocking(base, &masterXfer);
+}
+
+void BOARD_Accel_I2C_Init(void)
+{
+    BOARD_I2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
+{
+    uint8_t data = (uint8_t)txBuff;
+
+    return BOARD_I2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
+}
+
+status_t BOARD_Accel_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+    return BOARD_I2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
+}
+
+void BOARD_Codec_I2C_Init(void)
+{
+    BOARD_I2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Codec_I2C_Send(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
+{
+    return BOARD_I2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
+                          txBuffSize);
+}
+
+status_t BOARD_Codec_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+    return BOARD_I2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
+}
+#endif /* SDK_I2C_BASED_COMPONENT_USED */

example_code/i2c/polling_b2b/master/board.h

@@ -0,0 +1,230 @@
+/*
+ * Copyright 2017-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "clock_config.h"
+#include "fsl_common.h"
+#include "fsl_reset.h"
+#include "fsl_gpio.h"
+#include "fsl_iocon.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "LPCXpresso55S16"
+
+/*! @brief The UART to use for debug messages. */
+/* TODO: rename UART to USART */
+#define BOARD_DEBUG_UART_TYPE       kSerialPort_Uart
+#define BOARD_DEBUG_UART_BASEADDR   (uint32_t) USART0
+#define BOARD_DEBUG_UART_INSTANCE   0U
+#define BOARD_DEBUG_UART_CLK_FREQ   12000000U
+#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM0
+#define BOARD_DEBUG_UART_RST        kFC0_RST_SHIFT_RSTn
+#define BOARD_DEBUG_UART_CLKSRC     kCLOCK_Flexcomm0
+#define BOARD_UART_IRQ_HANDLER      FLEXCOMM0_IRQHandler
+#define BOARD_UART_IRQ              FLEXCOMM0_IRQn
+
+#define BOARD_ACCEL_I2C_BASEADDR   I2C4
+#define BOARD_ACCEL_I2C_CLOCK_FREQ 12000000
+
+#ifndef BOARD_DEBUG_UART_BAUDRATE
+#define BOARD_DEBUG_UART_BAUDRATE 115200U
+#endif /* BOARD_DEBUG_UART_BAUDRATE */
+
+#define BOARD_CODEC_I2C_BASEADDR   I2C4
+#define BOARD_CODEC_I2C_CLOCK_FREQ 12000000
+#define BOARD_CODEC_I2C_INSTANCE   4
+#ifndef BOARD_LED_RED_GPIO
+#define BOARD_LED_RED_GPIO GPIO
+#endif
+#define BOARD_LED_RED_GPIO_PORT 1U
+#ifndef BOARD_LED_RED_GPIO_PIN
+#define BOARD_LED_RED_GPIO_PIN 4U
+#endif
+
+#ifndef BOARD_LED_BLUE_GPIO
+#define BOARD_LED_BLUE_GPIO GPIO
+#endif
+#define BOARD_LED_BLUE_GPIO_PORT 1U
+#ifndef BOARD_LED_BLUE_GPIO_PIN
+#define BOARD_LED_BLUE_GPIO_PIN 6U
+#endif
+
+#ifndef BOARD_LED_GREEN_GPIO
+#define BOARD_LED_GREEN_GPIO GPIO
+#endif
+#define BOARD_LED_GREEN_GPIO_PORT 1U
+#ifndef BOARD_LED_GREEN_GPIO_PIN
+#define BOARD_LED_GREEN_GPIO_PIN 7U
+#endif
+
+#ifndef BOARD_SW1_GPIO
+#define BOARD_SW1_GPIO GPIO
+#endif
+#define BOARD_SW1_GPIO_PORT 1U
+#ifndef BOARD_SW1_GPIO_PIN
+#define BOARD_SW1_GPIO_PIN 18U
+#endif
+#define BOARD_SW1_NAME        "SW1"
+#define BOARD_SW1_IRQ         PIN_INT1_IRQn
+#define BOARD_SW1_IRQ_HANDLER PIN_INT1_IRQHandler
+
+#ifndef BOARD_SW3_GPIO
+#define BOARD_SW3_GPIO GPIO
+#endif
+#define BOARD_SW3_GPIO_PORT 1U
+#ifndef BOARD_SW3_GPIO_PIN
+#define BOARD_SW3_GPIO_PIN 9U
+#endif
+#define BOARD_SW3_NAME              "SW3"
+#define BOARD_SW3_IRQ               PIN_INT1_IRQn
+#define BOARD_SW3_IRQ_HANDLER       PIN_INT1_IRQHandler
+#define BOARD_SW3_GPIO_PININT_INDEX 1
+
+#ifndef BOARD_SW4_GPIO
+#define BOARD_SW4_GPIO GPIO
+#endif
+#define BOARD_SW4_GPIO_PORT 0U
+#ifndef BOARD_SW4_GPIO_PIN
+#define BOARD_SW4_GPIO_PIN 5U
+#endif
+#define BOARD_SW4_NAME              "SW4"
+#define BOARD_SW4_IRQ               PIN_INT0_IRQn
+#define BOARD_SW4_IRQ_HANDLER       PIN_INT0_IRQHandler
+#define BOARD_SW4_GPIO_PININT_INDEX 1
+
+/* USB PHY condfiguration */
+#define BOARD_USB_PHY_D_CAL     (0x05U)
+#define BOARD_USB_PHY_TXCAL45DP (0x0AU)
+#define BOARD_USB_PHY_TXCAL45DM (0x0AU)
+
+#define BOARD_SDIF_BASEADDR       SDIF
+#define BOARD_SDIF_CLKSRC         kCLOCK_SDio
+#define BOARD_SDIF_CLK_FREQ       CLOCK_GetSdioClkFreq()
+#define BOARD_SDIF_CLK_ATTACH     kMAIN_CLK_to_SDIO_CLK
+#define BOARD_SDIF_IRQ            SDIO_IRQn
+#define BOARD_MMC_VCC_SUPPLY      kMMC_VoltageWindows270to360
+#define BOARD_SD_CARD_DETECT_PIN  17
+#define BOARD_SD_CARD_DETECT_PORT 0
+#define BOARD_SD_CARD_DETECT_GPIO GPIO
+#define BOARD_SD_DETECT_TYPE      kSDMMCHOST_DetectCardByHostCD
+
+#define BOARD_SDIF_CD_GPIO_INIT()                                                                    \
+    {                                                                                                \
+        CLOCK_EnableClock(kCLOCK_Gpio2);                                                             \
+        GPIO_PinInit(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN, \
+                     &(gpio_pin_config_t){kGPIO_DigitalInput, 0U});                                  \
+    }
+#define BOARD_SDIF_CD_STATUS() \
+    GPIO_PinRead(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN)
+
+/* Board led color mapping */
+#define LOGIC_LED_ON  1U
+#define LOGIC_LED_OFF 0U
+
+#define BOARD_SDIF_CLK_ATTACH kMAIN_CLK_to_SDIO_CLK
+
+#define LED_RED_INIT(output)                                                                          \
+    {                                                                                                 \
+        IOCON_PinMuxSet(IOCON, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, IOCON_DIGITAL_EN);    \
+        GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN,             \
+                     &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \
+    }
+#define LED_RED_OFF()                                           \
+    GPIO_PortClear(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+                   1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED1 */
+#define LED_RED_ON()                                                                        \
+    GPIO_PortSet(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT,                               \
+                 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED1 \ \ \ \ \ \ \ \ \ \ \
+                                                */
+#define LED_RED_TOGGLE()                                         \
+    GPIO_PortToggle(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+                    1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED1 */
+
+#define LED_BLUE_INIT(output)                                                                         \
+    {                                                                                                 \
+        IOCON_PinMuxSet(IOCON, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, IOCON_DIGITAL_EN);  \
+        GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN,          \
+                     &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \
+    }
+#define LED_BLUE_OFF()                                            \
+    GPIO_PortClear(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                   1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED1 */
+#define LED_BLUE_ON()                                           \
+    GPIO_PortSet(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED1 */
+#define LED_BLUE_TOGGLE()                                          \
+    GPIO_PortToggle(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                    1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED1 */
+
+#define LED_GREEN_INIT(output)                                                              \
+    GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, BOARD_LED_GREEN_GPIO_PIN, \
+                 &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED1 */
+#define LED_GREEN_OFF()                                             \
+    GPIO_PortClear(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                   1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED1 */
+#define LED_GREEN_ON()                                            \
+    GPIO_PortSet(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED1 */
+#define LED_GREEN_TOGGLE()                                           \
+    GPIO_PortToggle(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                    1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED1 */
+
+/* Display. */
+#define BOARD_LCD_DC_GPIO      GPIO
+#define BOARD_LCD_DC_GPIO_PORT 1U
+#define BOARD_LCD_DC_GPIO_PIN  5U
+
+/* Serial MWM WIFI */
+#define BOARD_SERIAL_MWM_PORT_CLK_FREQ CLOCK_GetFlexCommClkFreq(2)
+#define BOARD_SERIAL_MWM_PORT          USART2
+#define BOARD_SERIAL_MWM_PORT_IRQn     FLEXCOMM2_IRQn
+#define BOARD_SERIAL_MWM_RST_WRITE(output)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz);
+status_t BOARD_I2C_Send(I2C_Type *base,
+                        uint8_t deviceAddress,
+                        uint32_t subAddress,
+                        uint8_t subaddressSize,
+                        uint8_t *txBuff,
+                        uint8_t txBuffSize);
+status_t BOARD_I2C_Receive(I2C_Type *base,
+                           uint8_t deviceAddress,
+                           uint32_t subAddress,
+                           uint8_t subaddressSize,
+                           uint8_t *rxBuff,
+                           uint8_t rxBuffSize);
+void BOARD_Accel_I2C_Init(void);
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
+status_t BOARD_Accel_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+void BOARD_Codec_I2C_Init(void);
+status_t BOARD_Codec_I2C_Send(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
+status_t BOARD_Codec_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */

example_code/i2c/polling_b2b/master/clock_config.c

@@ -0,0 +1,380 @@
+/*
+ * Copyright 2017-2018 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to set up clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up wait states of the flash.
+ *
+ * 3. Set up all dividers.
+ *
+ * 4. Set up all selectors to provide selected clocks.
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v7.0
+processor: LPC55S16
+package_id: LPC55S16JBD100
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+board: LPCXpresso55S16
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockPLL150M();
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 12 MHz}
+settings:
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    POWER_SetVoltageForFreq(12000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(12000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO12M */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF96M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF96M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    POWER_SetVoltageForFreq(96000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(96000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL100M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 100 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
+- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
+- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL100M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable High speed Crystal oscillator output to system  */
+
+    POWER_SetVoltageForFreq(100000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(100000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U),
+        .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
+        .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
+        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+        .pllRate = 100000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL150M
+called_from_default_init: true
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 150 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true}
+- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true}
+- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true}
+sources:
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL150M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable High speed Crystal oscillator output to system  */
+
+    POWER_SetVoltageForFreq(150000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(150000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
+        .pllndec = SYSCON_PLL0NDEC_NDIV(8U),
+        .pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
+        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+        .pllRate = 150000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockPLL1_150M ********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL1_150M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 150 MHz}
+settings:
+- {id: PLL1_Mode, value: Normal}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS}
+- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL1M_MULT.scale, value: '150', locked: true}
+- {id: SYSCON.PLL1N_DIV.scale, value: '8', locked: true}
+- {id: SYSCON.PLL1_PDEC.scale, value: '2', locked: true}
+sources:
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL1_150M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable High speed Crystal oscillator output to system  */
+
+    POWER_SetVoltageForFreq(150000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(150000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL1 */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL1);                    /*!< Switch PLL1CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL1);                  /* Ensure PLL is on  */
+    const pll_setup_t pll1Setup = {
+        .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(53U) | SYSCON_PLL1CTRL_SELP(31U),
+        .pllndec = SYSCON_PLL1NDEC_NDIV(8U),
+        .pllpdec = SYSCON_PLL1PDEC_PDIV(1U),
+        .pllmdec = SYSCON_PLL1MDEC_MDIV(150U),
+        .pllRate = 150000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL1Freq(&pll1Setup);                        /*!< Configure PLL1 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL1_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL1 */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK;
+#endif
+}
+

example_code/i2c/polling_b2b/master/clock_config.h

@@ -0,0 +1,173 @@
+/*
+ * Copyright 2017-2018 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         16000000U  /*!< Board xtal frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK         96000000U  /*!< Core clock frequency: 96000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF96M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL100M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         150000000U  /*!< Core clock frequency: 150000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockPLL1_150M ********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK       150000000U  /*!< Core clock frequency: 150000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL1_150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+

example_code/i2c/polling_b2b/master/i2c_polling_b2b_master.c

@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*  Standard C Included Files */
+#include <stdio.h>
+#include <string.h>
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_debug_console.h"
+#include "fsl_i2c.h"
+
+#include "fsl_power.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define EXAMPLE_I2C_MASTER_BASE    (I2C4_BASE)
+#define I2C_MASTER_CLOCK_FREQUENCY (12000000)
+#define WAIT_TIME                  10U
+#define EXAMPLE_I2C_MASTER ((I2C_Type *)EXAMPLE_I2C_MASTER_BASE)
+
+#define I2C_MASTER_SLAVE_ADDR_7BIT 0x7EU
+#define I2C_BAUDRATE               100000U
+#define I2C_DATA_LENGTH            33U
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+uint8_t g_master_txBuff[I2C_DATA_LENGTH];
+uint8_t g_master_rxBuff[I2C_DATA_LENGTH];
+
+/*******************************************************************************
+ * Code
+
+ ******************************************************************************/
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+    i2c_master_config_t masterConfig;
+    status_t reVal        = kStatus_Fail;
+    uint8_t deviceAddress = 0x01U;
+
+    /* set BOD VBAT level to 1.65V */
+    POWER_SetBodVbatLevel(kPOWER_BodVbatLevel1650mv, kPOWER_BodHystLevel50mv, false);
+    /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
+    CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+
+    /* attach 12 MHz clock to FLEXCOMM8 (I2C master) */
+    CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
+
+    /* reset FLEXCOMM for I2C */
+    RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn);
+
+    BOARD_InitBootPins();
+    BOARD_InitBootClocks();
+    BOARD_InitDebugConsole();
+
+    PRINTF("\r\nI2C board2board polling example -- Master transfer.\r\n");
+
+    /* Set up i2c master to send data to slave*/
+    /* First data in txBuff is data length of the transmiting data. */
+    g_master_txBuff[0] = I2C_DATA_LENGTH - 1U;
+    for (uint32_t i = 1U; i < I2C_DATA_LENGTH; i++)
+    {
+        g_master_txBuff[i] = i - 1;
+    }
+
+    PRINTF("Master will send data :");
+    for (uint32_t i = 0U; i < I2C_DATA_LENGTH - 1U; i++)
+    {
+        if (i % 8 == 0)
+        {
+            PRINTF("\r\n");
+        }
+        PRINTF("0x%2x  ", g_master_txBuff[i + 1]);
+    }
+    PRINTF("\r\n\r\n");
+
+    /*
+     * masterConfig.debugEnable = false;
+     * masterConfig.ignoreAck = false;
+     * masterConfig.pinConfig = kI2C_2PinOpenDrain;
+     * masterConfig.baudRate_Bps = 100000U;
+     * masterConfig.busIdleTimeout_ns = 0;
+     * masterConfig.pinLowTimeout_ns = 0;
+     * masterConfig.sdaGlitchFilterWidth_ns = 0;
+     * masterConfig.sclGlitchFilterWidth_ns = 0;
+     */
+    I2C_MasterGetDefaultConfig(&masterConfig);
+
+    /* Change the default baudrate configuration */
+    masterConfig.baudRate_Bps = I2C_BAUDRATE;
+
+    /* Initialize the I2C master peripheral */
+    I2C_MasterInit(EXAMPLE_I2C_MASTER, &masterConfig, I2C_MASTER_CLOCK_FREQUENCY);
+
+    /* Send master blocking data to slave */
+    if (kStatus_Success == I2C_MasterStart(EXAMPLE_I2C_MASTER, I2C_MASTER_SLAVE_ADDR_7BIT, kI2C_Write))
+    {
+        /* subAddress = 0x01, data = g_master_txBuff - write to slave.
+          start + slaveaddress(w) + subAddress + length of data buffer + data buffer + stop*/
+        reVal = I2C_MasterWriteBlocking(EXAMPLE_I2C_MASTER, &deviceAddress, 1, kI2C_TransferNoStopFlag);
+        if (reVal != kStatus_Success)
+        {
+            return -1;
+        }
+
+        reVal = I2C_MasterWriteBlocking(EXAMPLE_I2C_MASTER, g_master_txBuff, I2C_DATA_LENGTH, kI2C_TransferDefaultFlag);
+        if (reVal != kStatus_Success)
+        {
+            return -1;
+        }
+
+        reVal = I2C_MasterStop(EXAMPLE_I2C_MASTER);
+        if (reVal != kStatus_Success)
+        {
+            return -1;
+        }
+    }
+
+    /* Wait until the slave is ready for transmit, wait time depend on user's case.
+       Slave devices that need some time to process received byte or are not ready yet to
+       send the next byte, can pull the clock low to signal to the master that it should wait.*/
+    for (uint32_t i = 0U; i < WAIT_TIME; i++)
+    {
+        __NOP();
+    }
+
+    PRINTF("Receive sent data from slave :");
+
+    /* Receive blocking data from slave */
+    /* subAddress = 0x01, data = g_master_rxBuff - read from slave.
+      start + slaveaddress(w) + subAddress + repeated start + slaveaddress(r) + rx data buffer + stop */
+    if (kStatus_Success == I2C_MasterStart(EXAMPLE_I2C_MASTER, I2C_MASTER_SLAVE_ADDR_7BIT, kI2C_Write))
+    {
+        reVal = I2C_MasterWriteBlocking(EXAMPLE_I2C_MASTER, &deviceAddress, 1, kI2C_TransferNoStopFlag);
+        if (reVal != kStatus_Success)
+        {
+            return -1;
+        }
+
+        reVal = I2C_MasterRepeatedStart(EXAMPLE_I2C_MASTER, I2C_MASTER_SLAVE_ADDR_7BIT, kI2C_Read);
+        if (reVal != kStatus_Success)
+        {
+            return -1;
+        }
+
+        reVal =
+            I2C_MasterReadBlocking(EXAMPLE_I2C_MASTER, g_master_rxBuff, I2C_DATA_LENGTH - 1, kI2C_TransferDefaultFlag);
+        if (reVal != kStatus_Success)
+        {
+            return -1;
+        }
+
+        reVal = I2C_MasterStop(EXAMPLE_I2C_MASTER);
+        if (reVal != kStatus_Success)
+        {
+            return -1;
+        }
+    }
+
+    for (uint32_t i = 0U; i < I2C_DATA_LENGTH - 1; i++)
+    {
+        if (i % 8 == 0)
+        {
+            PRINTF("\r\n");
+        }
+        PRINTF("0x%2x  ", g_master_rxBuff[i]);
+    }
+    PRINTF("\r\n\r\n");
+
+    /* Transfer completed. Check the data.*/
+    for (uint32_t i = 0U; i < I2C_DATA_LENGTH - 1; i++)
+    {
+        if (g_master_rxBuff[i] != g_master_txBuff[i + 1])
+        {
+            PRINTF("\r\nError occurred in the transfer ! \r\n");
+            break;
+        }
+    }
+
+    PRINTF("\r\nEnd of I2C example .\r\n");
+    while (1)
+    {
+    }
+}

example_code/i2c/polling_b2b/master/i2c_polling_b2b_master_v3_9.xml

@@ -0,0 +1,124 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<ksdk:examples xmlns:ksdk="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd manifest.xsd">
+  <externalDefinitions>
+    <definition extID="utility.debug_console_lite.LPC55S16"/>
+    <definition extID="platform.utilities.assert_lite.LPC55S16"/>
+    <definition extID="platform.drivers.flexcomm_i2c.LPC55S16"/>
+    <definition extID="platform.drivers.common.LPC55S16"/>
+    <definition extID="platform.drivers.power.LPC55S16"/>
+    <definition extID="platform.drivers.lpc_iocon.LPC55S16"/>
+    <definition extID="platform.drivers.lpc_gpio.LPC55S16"/>
+    <definition extID="platform.drivers.inputmux.LPC55S16"/>
+    <definition extID="platform.drivers.clock.LPC55S16"/>
+    <definition extID="device.LPC55S16_CMSIS.LPC55S16"/>
+    <definition extID="device.LPC55S16_startup.LPC55S16"/>
+    <definition extID="platform.drivers.flexcomm_usart.LPC55S16"/>
+    <definition extID="platform.drivers.flexcomm.LPC55S16"/>
+    <definition extID="component.usart_adapter.LPC55S16"/>
+    <definition extID="component.lists.LPC55S16"/>
+    <definition extID="platform.drivers.reset.LPC55S16"/>
+    <definition extID="CMSIS_Include_core_cm.LPC55S16"/>
+    <definition extID="platform.drivers.inputmux_connections.LPC55S16"/>
+    <definition extID="platform.utilities.misc_utilities.LPC55S16"/>
+    <definition extID="device.LPC55S16_system.LPC55S16"/>
+    <definition extID="iar"/>
+    <definition extID="mdk"/>
+    <definition extID="armgcc"/>
+    <definition extID="mcuxpresso"/>
+    <definition extID="com.nxp.mcuxpresso"/>
+  </externalDefinitions>
+  <example id="lpcxpresso55s16_i2c_polling_b2b_master" name="i2c_polling_b2b_master" dependency="utility.debug_console_lite.LPC55S16 platform.utilities.assert_lite.LPC55S16 platform.drivers.flexcomm_i2c.LPC55S16 platform.drivers.common.LPC55S16 platform.drivers.power.LPC55S16 platform.drivers.lpc_iocon.LPC55S16 platform.drivers.lpc_gpio.LPC55S16 platform.drivers.inputmux.LPC55S16 platform.drivers.clock.LPC55S16 device.LPC55S16_CMSIS.LPC55S16 device.LPC55S16_startup.LPC55S16 platform.drivers.flexcomm_usart.LPC55S16 platform.drivers.flexcomm.LPC55S16 component.usart_adapter.LPC55S16 component.lists.LPC55S16 platform.drivers.reset.LPC55S16 CMSIS_Include_core_cm.LPC55S16 platform.drivers.inputmux_connections.LPC55S16 platform.utilities.misc_utilities.LPC55S16 device.LPC55S16_system.LPC55S16" category="driver_examples/i2c">
+    <projects>
+      <project type="com.crt.advproject.projecttype.exe" nature="org.eclipse.cdt.core.cnature"/>
+    </projects>
+    <toolchainSettings>
+      <toolchainSetting id_refs="com.nxp.mcuxpresso">
+        <option id="gnu.c.compiler.option.preprocessor.def.symbols" type="stringList">
+          <value>CPU_LPC55S16JBD100</value>
+          <value>MCUXPRESSO_SDK</value>
+        </option>
+        <option id="com.crt.advproject.gas.fpu" type="enum">
+          <value>com.crt.advproject.gas.fpu.fpv5sp.hard</value>
+        </option>
+        <option id="com.crt.advproject.gcc.fpu" type="enum">
+          <value>com.crt.advproject.gcc.fpu.fpv5sp.hard</value>
+        </option>
+        <option id="gnu.c.compiler.option.optimization.flags" type="string">
+          <value>-fno-common</value>
+        </option>
+        <option id="com.crt.advproject.c.misc.dialect" type="enum">
+          <value>com.crt.advproject.misc.dialect.gnu99</value>
+        </option>
+        <option id="gnu.c.compiler.option.misc.other" type="string">
+          <value>-mcpu=cortex-m33 -c -ffunction-sections -fdata-sections -ffreestanding -fno-builtin</value>
+        </option>
+        <option id="gnu.c.compiler.option.warnings.allwarn" type="boolean">
+          <value>false</value>
+        </option>
+        <option id="com.crt.advproject.link.fpu" type="enum">
+          <value>com.crt.advproject.link.fpu.fpv5sp.hard</value>
+        </option>
+        <option id="gnu.c.link.option.nostdlibs" type="boolean">
+          <value>true</value>
+        </option>
+      </toolchainSetting>
+    </toolchainSettings>
+    <include_paths>
+      <include_path path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/master" project_relative_path="board" type="c_include"/>
+    </include_paths>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/master/iar" project_relative_path="./" type="workspace" toolchain="iar">
+      <files mask="i2c_polling_b2b_master.ewd"/>
+      <files mask="i2c_polling_b2b_master.ewp"/>
+      <files mask="i2c_polling_b2b_master.eww"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/master/mdk" project_relative_path="./" type="workspace" toolchain="mdk">
+      <files mask="i2c_polling_b2b_master.uvprojx"/>
+      <files mask="i2c_polling_b2b_master.uvoptx"/>
+      <files mask="JLinkSettings.JLinkScript"/>
+      <files mask="JLinkSettings.ini"/>
+      <files mask="i2c_polling_b2b_master.uvmpw"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/master/armgcc" project_relative_path="./" type="workspace" toolchain="armgcc">
+      <files mask="build_all.bat"/>
+      <files mask="build_all.sh"/>
+      <files mask="clean.bat"/>
+      <files mask="clean.sh"/>
+      <files mask="CMakeLists.txt"/>
+      <files mask="flags.cmake"/>
+      <files mask="config.cmake"/>
+      <files mask="build_debug.bat"/>
+      <files mask="build_debug.sh"/>
+      <files mask="build_release.bat"/>
+      <files mask="build_release.sh"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/master" project_relative_path="source" type="src">
+      <files mask="i2c_polling_b2b_master.c"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/master" project_relative_path="board" type="src">
+      <files mask="pin_mux.c"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/master" project_relative_path="board" type="c_include">
+      <files mask="pin_mux.h"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/master" project_relative_path="board" type="src">
+      <files mask="board.c"/>
+      <files mask="clock_config.c"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/master" project_relative_path="board" type="c_include">
+      <files mask="board.h"/>
+      <files mask="clock_config.h"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/master" project_relative_path="doc" type="doc" toolchain="iar mdk mcuxpresso armgcc">
+      <files mask="readme.txt"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/master/iar" project_relative_path="LPC55S16/iar" type="linker" toolchain="iar">
+      <files mask="LPC55S16_flash.icf"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/master/mdk" project_relative_path="LPC55S16/arm" type="linker" toolchain="mdk">
+      <files mask="LPC55S16_flash.scf"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/master/armgcc" project_relative_path="LPC55S16/gcc" type="linker" toolchain="armgcc">
+      <files mask="LPC55S16_flash.ld"/>
+    </source>
+  </example>
+</ksdk:examples>

example_code/i2c/polling_b2b/master/pin_mux.c

@@ -0,0 +1,133 @@
+/*
+ * Copyright 2017-2020 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: LPC55S16
+package_id: LPC55S16JBD100
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_iocon.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29,
+    mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: inactive, slew_rate: standard,
+    invert: disabled, open_drain: disabled}
+  - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: inactive,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 */
+void BOARD_InitPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    const uint32_t port0_pin29_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
+                                         IOCON_PIO_FUNC1 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, 0U, 29U, port0_pin29_config);
+
+    const uint32_t port0_pin30_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
+                                         IOCON_PIO_FUNC1 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, 0U, 30U, port0_pin30_config);
+
+    const uint32_t port1_pin20_config = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */
+                                         IOCON_PIO_FUNC5 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, 1U, 20U, port1_pin20_config);
+
+    const uint32_t port1_pin21_config = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */
+                                         IOCON_PIO_FUNC5 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, 1U, 21U, port1_pin21_config);
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/

example_code/i2c/polling_b2b/master/pin_mux.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright 2017-2020 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC1 0x01u         /*!<@brief Selects pin function 1 */
+#define IOCON_PIO_FUNC5 0x05u         /*!<@brief Selects pin function 5 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u    /*!<@brief No addition pin function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/

example_code/i2c/polling_b2b/master/readme.txt

@@ -0,0 +1,69 @@
+Overview
+========
+The i2c_polling_b2b_master example shows how to use i2c driver as master to do board to board transfer
+using polling method:
+
+In this example, one i2c instance as master and another i2c instance on the other board as slave. Master sends a
+piece of data to slave, and receive a piece of data from slave. This example checks if the data received from
+slave is correct.
+
+Toolchain supported
+===================
+- IAR embedded Workbench  9.10.2
+- Keil MDK  5.34
+- GCC ARM Embedded  10.2.1
+- MCUXpresso  11.5.0
+
+Hardware requirements
+=====================
+- Micro USB cable
+- Two LPCXpresso55S16 boards
+- Personal Computer
+
+Board settings
+==============
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+MASTER_BOARD        CONNECTS TO         SLAVE_BOARD
+Pin Name   Board Location     Pin Name   Board Location
+I2C_SCL    J9-2               I2C_SCL    J9-2
+I2C_SDA    J9-4               I2C_SDA    J9-4
+GND        J9-8               GND        J9-8   
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The jumper setting:
+    Default jumpers configuration does not work,  you will need to add JP20 and JP21 (JP22 optional for ADC use)
+    
+Prepare the Demo
+================
+1. Connect a micro USB cable between the PC host and the LPC-Link USB port (J1) on the board.
+2. Open a serial terminal on PC for JLink serial device with these settings:
+   - 115200 baud rate
+   - 8 data bits
+   - No parity
+   - One stop bit
+   - No flow control
+3. Download the program to the target board.
+4. Either press the reset button on your board or launch the debugger in your IDE to begin running
+   the demo.
+
+Running the demo
+================
+The following message shows in the terminal if the example runs successfully.
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+I2C board2board polling example -- Master transfer.
+Master will send data :
+0x 0  0x 1  0x 2  0x 3  0x 4  0x 5  0x 6  0x 7  
+0x 8  0x 9  0x a  0x b  0x c  0x d  0x e  0x f  
+0x10  0x11  0x12  0x13  0x14  0x15  0x16  0x17  
+0x18  0x19  0x1a  0x1b  0x1c  0x1d  0x1e  0x1f  
+
+Receive sent data from slave :
+0x 0  0x 1  0x 2  0x 3  0x 4  0x 5  0x 6  0x 7  
+0x 8  0x 9  0x a  0x b  0x c  0x d  0x e  0x f  
+0x10  0x11  0x12  0x13  0x14  0x15  0x16  0x17  
+0x18  0x19  0x1a  0x1b  0x1c  0x1d  0x1e  0x1f  
+
+
+End of I2C example .
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~

example_code/i2c/polling_b2b/slave/board.c

@@ -0,0 +1,122 @@
+/*
+ * Copyright 2017-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "board.h"
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+#include "fsl_i2c.h"
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+    /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
+    CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+
+    RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST);
+
+    uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+
+    DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz)
+{
+    i2c_master_config_t i2cConfig = {0};
+
+    I2C_MasterGetDefaultConfig(&i2cConfig);
+    I2C_MasterInit(base, &i2cConfig, clkSrc_Hz);
+}
+
+status_t BOARD_I2C_Send(I2C_Type *base,
+                        uint8_t deviceAddress,
+                        uint32_t subAddress,
+                        uint8_t subaddressSize,
+                        uint8_t *txBuff,
+                        uint8_t txBuffSize)
+{
+    i2c_master_transfer_t masterXfer;
+
+    /* Prepare transfer structure. */
+    masterXfer.slaveAddress   = deviceAddress;
+    masterXfer.direction      = kI2C_Write;
+    masterXfer.subaddress     = subAddress;
+    masterXfer.subaddressSize = subaddressSize;
+    masterXfer.data           = txBuff;
+    masterXfer.dataSize       = txBuffSize;
+    masterXfer.flags          = kI2C_TransferDefaultFlag;
+
+    return I2C_MasterTransferBlocking(base, &masterXfer);
+}
+
+status_t BOARD_I2C_Receive(I2C_Type *base,
+                           uint8_t deviceAddress,
+                           uint32_t subAddress,
+                           uint8_t subaddressSize,
+                           uint8_t *rxBuff,
+                           uint8_t rxBuffSize)
+{
+    i2c_master_transfer_t masterXfer;
+
+    /* Prepare transfer structure. */
+    masterXfer.slaveAddress   = deviceAddress;
+    masterXfer.subaddress     = subAddress;
+    masterXfer.subaddressSize = subaddressSize;
+    masterXfer.data           = rxBuff;
+    masterXfer.dataSize       = rxBuffSize;
+    masterXfer.direction      = kI2C_Read;
+    masterXfer.flags          = kI2C_TransferDefaultFlag;
+
+    return I2C_MasterTransferBlocking(base, &masterXfer);
+}
+
+void BOARD_Accel_I2C_Init(void)
+{
+    BOARD_I2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
+{
+    uint8_t data = (uint8_t)txBuff;
+
+    return BOARD_I2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
+}
+
+status_t BOARD_Accel_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+    return BOARD_I2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
+}
+
+void BOARD_Codec_I2C_Init(void)
+{
+    BOARD_I2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Codec_I2C_Send(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
+{
+    return BOARD_I2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
+                          txBuffSize);
+}
+
+status_t BOARD_Codec_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+    return BOARD_I2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
+}
+#endif /* SDK_I2C_BASED_COMPONENT_USED */

example_code/i2c/polling_b2b/slave/board.h

@@ -0,0 +1,230 @@
+/*
+ * Copyright 2017-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "clock_config.h"
+#include "fsl_common.h"
+#include "fsl_reset.h"
+#include "fsl_gpio.h"
+#include "fsl_iocon.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "LPCXpresso55S16"
+
+/*! @brief The UART to use for debug messages. */
+/* TODO: rename UART to USART */
+#define BOARD_DEBUG_UART_TYPE       kSerialPort_Uart
+#define BOARD_DEBUG_UART_BASEADDR   (uint32_t) USART0
+#define BOARD_DEBUG_UART_INSTANCE   0U
+#define BOARD_DEBUG_UART_CLK_FREQ   12000000U
+#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM0
+#define BOARD_DEBUG_UART_RST        kFC0_RST_SHIFT_RSTn
+#define BOARD_DEBUG_UART_CLKSRC     kCLOCK_Flexcomm0
+#define BOARD_UART_IRQ_HANDLER      FLEXCOMM0_IRQHandler
+#define BOARD_UART_IRQ              FLEXCOMM0_IRQn
+
+#define BOARD_ACCEL_I2C_BASEADDR   I2C4
+#define BOARD_ACCEL_I2C_CLOCK_FREQ 12000000
+
+#ifndef BOARD_DEBUG_UART_BAUDRATE
+#define BOARD_DEBUG_UART_BAUDRATE 115200U
+#endif /* BOARD_DEBUG_UART_BAUDRATE */
+
+#define BOARD_CODEC_I2C_BASEADDR   I2C4
+#define BOARD_CODEC_I2C_CLOCK_FREQ 12000000
+#define BOARD_CODEC_I2C_INSTANCE   4
+#ifndef BOARD_LED_RED_GPIO
+#define BOARD_LED_RED_GPIO GPIO
+#endif
+#define BOARD_LED_RED_GPIO_PORT 1U
+#ifndef BOARD_LED_RED_GPIO_PIN
+#define BOARD_LED_RED_GPIO_PIN 4U
+#endif
+
+#ifndef BOARD_LED_BLUE_GPIO
+#define BOARD_LED_BLUE_GPIO GPIO
+#endif
+#define BOARD_LED_BLUE_GPIO_PORT 1U
+#ifndef BOARD_LED_BLUE_GPIO_PIN
+#define BOARD_LED_BLUE_GPIO_PIN 6U
+#endif
+
+#ifndef BOARD_LED_GREEN_GPIO
+#define BOARD_LED_GREEN_GPIO GPIO
+#endif
+#define BOARD_LED_GREEN_GPIO_PORT 1U
+#ifndef BOARD_LED_GREEN_GPIO_PIN
+#define BOARD_LED_GREEN_GPIO_PIN 7U
+#endif
+
+#ifndef BOARD_SW1_GPIO
+#define BOARD_SW1_GPIO GPIO
+#endif
+#define BOARD_SW1_GPIO_PORT 1U
+#ifndef BOARD_SW1_GPIO_PIN
+#define BOARD_SW1_GPIO_PIN 18U
+#endif
+#define BOARD_SW1_NAME        "SW1"
+#define BOARD_SW1_IRQ         PIN_INT1_IRQn
+#define BOARD_SW1_IRQ_HANDLER PIN_INT1_IRQHandler
+
+#ifndef BOARD_SW3_GPIO
+#define BOARD_SW3_GPIO GPIO
+#endif
+#define BOARD_SW3_GPIO_PORT 1U
+#ifndef BOARD_SW3_GPIO_PIN
+#define BOARD_SW3_GPIO_PIN 9U
+#endif
+#define BOARD_SW3_NAME              "SW3"
+#define BOARD_SW3_IRQ               PIN_INT1_IRQn
+#define BOARD_SW3_IRQ_HANDLER       PIN_INT1_IRQHandler
+#define BOARD_SW3_GPIO_PININT_INDEX 1
+
+#ifndef BOARD_SW4_GPIO
+#define BOARD_SW4_GPIO GPIO
+#endif
+#define BOARD_SW4_GPIO_PORT 0U
+#ifndef BOARD_SW4_GPIO_PIN
+#define BOARD_SW4_GPIO_PIN 5U
+#endif
+#define BOARD_SW4_NAME              "SW4"
+#define BOARD_SW4_IRQ               PIN_INT0_IRQn
+#define BOARD_SW4_IRQ_HANDLER       PIN_INT0_IRQHandler
+#define BOARD_SW4_GPIO_PININT_INDEX 1
+
+/* USB PHY condfiguration */
+#define BOARD_USB_PHY_D_CAL     (0x05U)
+#define BOARD_USB_PHY_TXCAL45DP (0x0AU)
+#define BOARD_USB_PHY_TXCAL45DM (0x0AU)
+
+#define BOARD_SDIF_BASEADDR       SDIF
+#define BOARD_SDIF_CLKSRC         kCLOCK_SDio
+#define BOARD_SDIF_CLK_FREQ       CLOCK_GetSdioClkFreq()
+#define BOARD_SDIF_CLK_ATTACH     kMAIN_CLK_to_SDIO_CLK
+#define BOARD_SDIF_IRQ            SDIO_IRQn
+#define BOARD_MMC_VCC_SUPPLY      kMMC_VoltageWindows270to360
+#define BOARD_SD_CARD_DETECT_PIN  17
+#define BOARD_SD_CARD_DETECT_PORT 0
+#define BOARD_SD_CARD_DETECT_GPIO GPIO
+#define BOARD_SD_DETECT_TYPE      kSDMMCHOST_DetectCardByHostCD
+
+#define BOARD_SDIF_CD_GPIO_INIT()                                                                    \
+    {                                                                                                \
+        CLOCK_EnableClock(kCLOCK_Gpio2);                                                             \
+        GPIO_PinInit(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN, \
+                     &(gpio_pin_config_t){kGPIO_DigitalInput, 0U});                                  \
+    }
+#define BOARD_SDIF_CD_STATUS() \
+    GPIO_PinRead(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN)
+
+/* Board led color mapping */
+#define LOGIC_LED_ON  1U
+#define LOGIC_LED_OFF 0U
+
+#define BOARD_SDIF_CLK_ATTACH kMAIN_CLK_to_SDIO_CLK
+
+#define LED_RED_INIT(output)                                                                          \
+    {                                                                                                 \
+        IOCON_PinMuxSet(IOCON, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, IOCON_DIGITAL_EN);    \
+        GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN,             \
+                     &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \
+    }
+#define LED_RED_OFF()                                           \
+    GPIO_PortClear(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+                   1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED1 */
+#define LED_RED_ON()                                                                        \
+    GPIO_PortSet(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT,                               \
+                 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED1 \ \ \ \ \ \ \ \ \ \ \
+                                                */
+#define LED_RED_TOGGLE()                                         \
+    GPIO_PortToggle(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+                    1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED1 */
+
+#define LED_BLUE_INIT(output)                                                                         \
+    {                                                                                                 \
+        IOCON_PinMuxSet(IOCON, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, IOCON_DIGITAL_EN);  \
+        GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN,          \
+                     &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \
+    }
+#define LED_BLUE_OFF()                                            \
+    GPIO_PortClear(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                   1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED1 */
+#define LED_BLUE_ON()                                           \
+    GPIO_PortSet(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED1 */
+#define LED_BLUE_TOGGLE()                                          \
+    GPIO_PortToggle(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                    1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED1 */
+
+#define LED_GREEN_INIT(output)                                                              \
+    GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, BOARD_LED_GREEN_GPIO_PIN, \
+                 &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED1 */
+#define LED_GREEN_OFF()                                             \
+    GPIO_PortClear(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                   1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED1 */
+#define LED_GREEN_ON()                                            \
+    GPIO_PortSet(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED1 */
+#define LED_GREEN_TOGGLE()                                           \
+    GPIO_PortToggle(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                    1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED1 */
+
+/* Display. */
+#define BOARD_LCD_DC_GPIO      GPIO
+#define BOARD_LCD_DC_GPIO_PORT 1U
+#define BOARD_LCD_DC_GPIO_PIN  5U
+
+/* Serial MWM WIFI */
+#define BOARD_SERIAL_MWM_PORT_CLK_FREQ CLOCK_GetFlexCommClkFreq(2)
+#define BOARD_SERIAL_MWM_PORT          USART2
+#define BOARD_SERIAL_MWM_PORT_IRQn     FLEXCOMM2_IRQn
+#define BOARD_SERIAL_MWM_RST_WRITE(output)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz);
+status_t BOARD_I2C_Send(I2C_Type *base,
+                        uint8_t deviceAddress,
+                        uint32_t subAddress,
+                        uint8_t subaddressSize,
+                        uint8_t *txBuff,
+                        uint8_t txBuffSize);
+status_t BOARD_I2C_Receive(I2C_Type *base,
+                           uint8_t deviceAddress,
+                           uint32_t subAddress,
+                           uint8_t subaddressSize,
+                           uint8_t *rxBuff,
+                           uint8_t rxBuffSize);
+void BOARD_Accel_I2C_Init(void);
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
+status_t BOARD_Accel_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+void BOARD_Codec_I2C_Init(void);
+status_t BOARD_Codec_I2C_Send(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
+status_t BOARD_Codec_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */

example_code/i2c/polling_b2b/slave/clock_config.c

@@ -0,0 +1,380 @@
+/*
+ * Copyright 2017-2018 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to set up clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up wait states of the flash.
+ *
+ * 3. Set up all dividers.
+ *
+ * 4. Set up all selectors to provide selected clocks.
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v7.0
+processor: LPC55S16
+package_id: LPC55S16JBD100
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+board: LPCXpresso55S16
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockPLL150M();
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 12 MHz}
+settings:
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    POWER_SetVoltageForFreq(12000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(12000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO12M */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF96M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF96M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    POWER_SetVoltageForFreq(96000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(96000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL100M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 100 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
+- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
+- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL100M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable High speed Crystal oscillator output to system  */
+
+    POWER_SetVoltageForFreq(100000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(100000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U),
+        .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
+        .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
+        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+        .pllRate = 100000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL150M
+called_from_default_init: true
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 150 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true}
+- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true}
+- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true}
+sources:
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL150M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable High speed Crystal oscillator output to system  */
+
+    POWER_SetVoltageForFreq(150000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(150000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
+        .pllndec = SYSCON_PLL0NDEC_NDIV(8U),
+        .pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
+        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+        .pllRate = 150000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockPLL1_150M ********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL1_150M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 150 MHz}
+settings:
+- {id: PLL1_Mode, value: Normal}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS}
+- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL1M_MULT.scale, value: '150', locked: true}
+- {id: SYSCON.PLL1N_DIV.scale, value: '8', locked: true}
+- {id: SYSCON.PLL1_PDEC.scale, value: '2', locked: true}
+sources:
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL1_150M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable High speed Crystal oscillator output to system  */
+
+    POWER_SetVoltageForFreq(150000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(150000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL1 */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL1);                    /*!< Switch PLL1CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL1);                  /* Ensure PLL is on  */
+    const pll_setup_t pll1Setup = {
+        .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(53U) | SYSCON_PLL1CTRL_SELP(31U),
+        .pllndec = SYSCON_PLL1NDEC_NDIV(8U),
+        .pllpdec = SYSCON_PLL1PDEC_PDIV(1U),
+        .pllmdec = SYSCON_PLL1MDEC_MDIV(150U),
+        .pllRate = 150000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL1Freq(&pll1Setup);                        /*!< Configure PLL1 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL1_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL1 */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK;
+#endif
+}
+

example_code/i2c/polling_b2b/slave/clock_config.h

@@ -0,0 +1,173 @@
+/*
+ * Copyright 2017-2018 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         16000000U  /*!< Board xtal frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK         96000000U  /*!< Core clock frequency: 96000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF96M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL100M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         150000000U  /*!< Core clock frequency: 150000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockPLL1_150M ********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK       150000000U  /*!< Core clock frequency: 150000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL1_150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+

example_code/i2c/polling_b2b/slave/i2c_polling_b2b_slave.c

@@ -0,0 +1,114 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*  Standard C Included Files */
+#include <stdio.h>
+#include <string.h>
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_debug_console.h"
+#include "fsl_i2c.h"
+
+#include "fsl_power.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define EXAMPLE_I2C_SLAVE_BASE    (I2C4_BASE)
+#define I2C_SLAVE_CLOCK_FREQUENCY (12000000)
+#define EXAMPLE_I2C_SLAVE ((I2C_Type *)EXAMPLE_I2C_SLAVE_BASE)
+
+#define I2C_MASTER_SLAVE_ADDR_7BIT 0x7EU
+#define I2C_DATA_LENGTH            34U
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+uint8_t g_slave_buff[I2C_DATA_LENGTH];
+
+/*******************************************************************************
+ * Code
+
+ ******************************************************************************/
+
+int main(void)
+{
+    i2c_slave_config_t slaveConfig;
+    status_t reVal = kStatus_Fail;
+    uint8_t subaddress;
+
+    /* set BOD VBAT level to 1.65V */
+    POWER_SetBodVbatLevel(kPOWER_BodVbatLevel1650mv, kPOWER_BodHystLevel50mv, false);
+    /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
+    CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+
+    /* attach 12 MHz clock to FLEXCOMM8 (I2C slave) */
+    CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
+
+    /* reset FLEXCOMM for I2C */
+    RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn);
+
+    BOARD_InitBootPins();
+    BOARD_InitBootClocks();
+    BOARD_InitDebugConsole();
+
+    PRINTF("\r\nI2C board2board polling example -- Slave transfer.\r\n\r\n");
+
+    /* Set up i2c slave first*/
+    I2C_SlaveGetDefaultConfig(&slaveConfig);
+
+    /* Change the slave address */
+    slaveConfig.address0.address = I2C_MASTER_SLAVE_ADDR_7BIT;
+
+    /* Initialize the I2C slave peripheral */
+    I2C_SlaveInit(EXAMPLE_I2C_SLAVE, &slaveConfig, I2C_SLAVE_CLOCK_FREQUENCY);
+
+    memset(g_slave_buff, 0, sizeof(g_slave_buff));
+
+    /* Start accepting I2C transfers on the I2C slave peripheral */
+    reVal = I2C_SlaveReadBlocking(EXAMPLE_I2C_SLAVE, g_slave_buff, I2C_DATA_LENGTH);
+
+    if (reVal != kStatus_Success)
+    {
+        return -1;
+    }
+
+    /* Start accepting I2C transfers on the I2C slave peripheral to simulate subaddress and will send ACK to master */
+    reVal = I2C_SlaveReadBlocking(EXAMPLE_I2C_SLAVE, &subaddress, 1);
+
+    if (reVal != kStatus_Success)
+    {
+        return -1;
+    }
+
+    reVal = I2C_SlaveWriteBlocking(EXAMPLE_I2C_SLAVE, &g_slave_buff[2], g_slave_buff[1]);
+
+    if (reVal != kStatus_Success)
+    {
+        return -1;
+    }
+
+    PRINTF("Slave received data :");
+    for (uint32_t i = 0U; i < g_slave_buff[1]; i++)
+    {
+        if (i % 8 == 0)
+        {
+            PRINTF("\r\n");
+        }
+        PRINTF("0x%2x  ", g_slave_buff[2 + i]);
+    }
+    PRINTF("\r\n\r\n");
+
+    PRINTF("\r\nEnd of I2C example .\r\n");
+
+    while (1)
+    {
+    }
+}

example_code/i2c/polling_b2b/slave/i2c_polling_b2b_slave_v3_9.xml

@@ -0,0 +1,124 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<ksdk:examples xmlns:ksdk="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd manifest.xsd">
+  <externalDefinitions>
+    <definition extID="utility.debug_console_lite.LPC55S16"/>
+    <definition extID="platform.utilities.assert_lite.LPC55S16"/>
+    <definition extID="platform.drivers.flexcomm_i2c.LPC55S16"/>
+    <definition extID="platform.drivers.common.LPC55S16"/>
+    <definition extID="platform.drivers.power.LPC55S16"/>
+    <definition extID="platform.drivers.lpc_iocon.LPC55S16"/>
+    <definition extID="platform.drivers.lpc_gpio.LPC55S16"/>
+    <definition extID="platform.drivers.inputmux.LPC55S16"/>
+    <definition extID="platform.drivers.clock.LPC55S16"/>
+    <definition extID="device.LPC55S16_CMSIS.LPC55S16"/>
+    <definition extID="device.LPC55S16_startup.LPC55S16"/>
+    <definition extID="platform.drivers.flexcomm_usart.LPC55S16"/>
+    <definition extID="platform.drivers.flexcomm.LPC55S16"/>
+    <definition extID="component.usart_adapter.LPC55S16"/>
+    <definition extID="component.lists.LPC55S16"/>
+    <definition extID="platform.drivers.reset.LPC55S16"/>
+    <definition extID="CMSIS_Include_core_cm.LPC55S16"/>
+    <definition extID="platform.drivers.inputmux_connections.LPC55S16"/>
+    <definition extID="platform.utilities.misc_utilities.LPC55S16"/>
+    <definition extID="device.LPC55S16_system.LPC55S16"/>
+    <definition extID="iar"/>
+    <definition extID="mdk"/>
+    <definition extID="armgcc"/>
+    <definition extID="mcuxpresso"/>
+    <definition extID="com.nxp.mcuxpresso"/>
+  </externalDefinitions>
+  <example id="lpcxpresso55s16_i2c_polling_b2b_slave" name="i2c_polling_b2b_slave" dependency="utility.debug_console_lite.LPC55S16 platform.utilities.assert_lite.LPC55S16 platform.drivers.flexcomm_i2c.LPC55S16 platform.drivers.common.LPC55S16 platform.drivers.power.LPC55S16 platform.drivers.lpc_iocon.LPC55S16 platform.drivers.lpc_gpio.LPC55S16 platform.drivers.inputmux.LPC55S16 platform.drivers.clock.LPC55S16 device.LPC55S16_CMSIS.LPC55S16 device.LPC55S16_startup.LPC55S16 platform.drivers.flexcomm_usart.LPC55S16 platform.drivers.flexcomm.LPC55S16 component.usart_adapter.LPC55S16 component.lists.LPC55S16 platform.drivers.reset.LPC55S16 CMSIS_Include_core_cm.LPC55S16 platform.drivers.inputmux_connections.LPC55S16 platform.utilities.misc_utilities.LPC55S16 device.LPC55S16_system.LPC55S16" category="driver_examples/i2c">
+    <projects>
+      <project type="com.crt.advproject.projecttype.exe" nature="org.eclipse.cdt.core.cnature"/>
+    </projects>
+    <toolchainSettings>
+      <toolchainSetting id_refs="com.nxp.mcuxpresso">
+        <option id="gnu.c.compiler.option.preprocessor.def.symbols" type="stringList">
+          <value>CPU_LPC55S16JBD100</value>
+          <value>MCUXPRESSO_SDK</value>
+        </option>
+        <option id="com.crt.advproject.gas.fpu" type="enum">
+          <value>com.crt.advproject.gas.fpu.fpv5sp.hard</value>
+        </option>
+        <option id="com.crt.advproject.gcc.fpu" type="enum">
+          <value>com.crt.advproject.gcc.fpu.fpv5sp.hard</value>
+        </option>
+        <option id="gnu.c.compiler.option.optimization.flags" type="string">
+          <value>-fno-common</value>
+        </option>
+        <option id="com.crt.advproject.c.misc.dialect" type="enum">
+          <value>com.crt.advproject.misc.dialect.gnu99</value>
+        </option>
+        <option id="gnu.c.compiler.option.misc.other" type="string">
+          <value>-mcpu=cortex-m33 -c -ffunction-sections -fdata-sections -ffreestanding -fno-builtin</value>
+        </option>
+        <option id="gnu.c.compiler.option.warnings.allwarn" type="boolean">
+          <value>false</value>
+        </option>
+        <option id="com.crt.advproject.link.fpu" type="enum">
+          <value>com.crt.advproject.link.fpu.fpv5sp.hard</value>
+        </option>
+        <option id="gnu.c.link.option.nostdlibs" type="boolean">
+          <value>true</value>
+        </option>
+      </toolchainSetting>
+    </toolchainSettings>
+    <include_paths>
+      <include_path path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/slave" project_relative_path="board" type="c_include"/>
+    </include_paths>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/slave/iar" project_relative_path="./" type="workspace" toolchain="iar">
+      <files mask="i2c_polling_b2b_slave.ewd"/>
+      <files mask="i2c_polling_b2b_slave.ewp"/>
+      <files mask="i2c_polling_b2b_slave.eww"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/slave/mdk" project_relative_path="./" type="workspace" toolchain="mdk">
+      <files mask="i2c_polling_b2b_slave.uvprojx"/>
+      <files mask="i2c_polling_b2b_slave.uvoptx"/>
+      <files mask="JLinkSettings.JLinkScript"/>
+      <files mask="JLinkSettings.ini"/>
+      <files mask="i2c_polling_b2b_slave.uvmpw"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/slave/armgcc" project_relative_path="./" type="workspace" toolchain="armgcc">
+      <files mask="build_all.bat"/>
+      <files mask="build_all.sh"/>
+      <files mask="clean.bat"/>
+      <files mask="clean.sh"/>
+      <files mask="CMakeLists.txt"/>
+      <files mask="flags.cmake"/>
+      <files mask="config.cmake"/>
+      <files mask="build_debug.bat"/>
+      <files mask="build_debug.sh"/>
+      <files mask="build_release.bat"/>
+      <files mask="build_release.sh"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/slave" project_relative_path="source" type="src">
+      <files mask="i2c_polling_b2b_slave.c"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/slave" project_relative_path="board" type="src">
+      <files mask="pin_mux.c"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/slave" project_relative_path="board" type="c_include">
+      <files mask="pin_mux.h"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/slave" project_relative_path="board" type="src">
+      <files mask="board.c"/>
+      <files mask="clock_config.c"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/slave" project_relative_path="board" type="c_include">
+      <files mask="board.h"/>
+      <files mask="clock_config.h"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/slave" project_relative_path="doc" type="doc" toolchain="iar mdk mcuxpresso armgcc">
+      <files mask="readme.txt"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/slave/iar" project_relative_path="LPC55S16/iar" type="linker" toolchain="iar">
+      <files mask="LPC55S16_flash.icf"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/slave/mdk" project_relative_path="LPC55S16/arm" type="linker" toolchain="mdk">
+      <files mask="LPC55S16_flash.scf"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/polling_b2b/slave/armgcc" project_relative_path="LPC55S16/gcc" type="linker" toolchain="armgcc">
+      <files mask="LPC55S16_flash.ld"/>
+    </source>
+  </example>
+</ksdk:examples>

example_code/i2c/polling_b2b/slave/pin_mux.c

@@ -0,0 +1,133 @@
+/*
+ * Copyright 2017-2020 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: LPC55S16
+package_id: LPC55S16JBD100
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_iocon.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29,
+    mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: inactive, slew_rate: standard,
+    invert: disabled, open_drain: disabled}
+  - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: inactive,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 */
+void BOARD_InitPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    const uint32_t port0_pin29_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
+                                         IOCON_PIO_FUNC1 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, 0U, 29U, port0_pin29_config);
+
+    const uint32_t port0_pin30_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
+                                         IOCON_PIO_FUNC1 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, 0U, 30U, port0_pin30_config);
+
+    const uint32_t port1_pin20_config = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */
+                                         IOCON_PIO_FUNC5 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, 1U, 20U, port1_pin20_config);
+
+    const uint32_t port1_pin21_config = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */
+                                         IOCON_PIO_FUNC5 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, 1U, 21U, port1_pin21_config);
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/

example_code/i2c/polling_b2b/slave/pin_mux.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright 2017-2020 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC1 0x01u         /*!<@brief Selects pin function 1 */
+#define IOCON_PIO_FUNC5 0x05u         /*!<@brief Selects pin function 5 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u    /*!<@brief No addition pin function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/

example_code/i2c/polling_b2b/slave/readme.txt

@@ -0,0 +1,65 @@
+Overview
+========
+The i2c_polling_b2b_slave example shows how to use i2c driver as slave to do board to board transfer
+with a polling master:
+
+In this example, one i2c instance as slave and another i2c instance on the other board as master. Master sends a
+piece of data to slave, and receive a piece of data from slave. This example checks if the data received from
+slave is correct.
+
+Toolchain supported
+===================
+- IAR embedded Workbench  9.10.2
+- Keil MDK  5.34
+- GCC ARM Embedded  10.2.1
+- MCUXpresso  11.5.0
+
+Hardware requirements
+=====================
+- Micro USB cable 
+- Two LPCXpresso55S16 boards
+- Personal Computer
+
+Board settings
+==============
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+MASTER_BOARD        CONNECTS TO         SLAVE_BOARD
+Pin Name   Board Location     Pin Name   Board Location
+I2C_SCL    J9-2               I2C_SCL    J9-2
+I2C_SDA    J9-4               I2C_SDA    J9-4
+GND        J9-8               GND        J9-8   
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The jumper setting:
+    Default jumpers configuration does not work,  you will need to add JP20 and JP21 (JP22 optional for ADC use)
+    
+Prepare the Demo
+================
+1. Connect a micro USB cable between the PC host and the LPC-Link USB port (J1) on the board.
+2. Open a serial terminal on PC for JLink serial device with these settings:
+   - 115200 baud rate
+   - 8 data bits
+   - No parity
+   - One stop bit
+   - No flow control
+3. Download the program to the target board.
+4. Either press the reset button on your board or launch the debugger in your IDE to begin running
+   the demo.
+
+Running the demo
+================
+The following message shows in the terminal if the example runs successfully.
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+I2C board2board polling example -- Slave transfer.
+
+
+Slave received data :
+0x 0  0x 1  0x 2  0x 3  0x 4  0x 5  0x 6  0x 7
+0x 8  0x 9  0x a  0x b  0x c  0x d  0x e  0x f
+0x10  0x11  0x12  0x13  0x14  0x15  0x16  0x17
+0x18  0x19  0x1a  0x1b  0x1c  0x1d  0x1e  0x1f
+
+
+End of I2C example .
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~

example_code/i2c/read_accel_value_transfer/board.c

@@ -0,0 +1,122 @@
+/*
+ * Copyright 2017-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "board.h"
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+#include "fsl_i2c.h"
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+    /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
+    CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+
+    RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST);
+
+    uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+
+    DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz)
+{
+    i2c_master_config_t i2cConfig = {0};
+
+    I2C_MasterGetDefaultConfig(&i2cConfig);
+    I2C_MasterInit(base, &i2cConfig, clkSrc_Hz);
+}
+
+status_t BOARD_I2C_Send(I2C_Type *base,
+                        uint8_t deviceAddress,
+                        uint32_t subAddress,
+                        uint8_t subaddressSize,
+                        uint8_t *txBuff,
+                        uint8_t txBuffSize)
+{
+    i2c_master_transfer_t masterXfer;
+
+    /* Prepare transfer structure. */
+    masterXfer.slaveAddress   = deviceAddress;
+    masterXfer.direction      = kI2C_Write;
+    masterXfer.subaddress     = subAddress;
+    masterXfer.subaddressSize = subaddressSize;
+    masterXfer.data           = txBuff;
+    masterXfer.dataSize       = txBuffSize;
+    masterXfer.flags          = kI2C_TransferDefaultFlag;
+
+    return I2C_MasterTransferBlocking(base, &masterXfer);
+}
+
+status_t BOARD_I2C_Receive(I2C_Type *base,
+                           uint8_t deviceAddress,
+                           uint32_t subAddress,
+                           uint8_t subaddressSize,
+                           uint8_t *rxBuff,
+                           uint8_t rxBuffSize)
+{
+    i2c_master_transfer_t masterXfer;
+
+    /* Prepare transfer structure. */
+    masterXfer.slaveAddress   = deviceAddress;
+    masterXfer.subaddress     = subAddress;
+    masterXfer.subaddressSize = subaddressSize;
+    masterXfer.data           = rxBuff;
+    masterXfer.dataSize       = rxBuffSize;
+    masterXfer.direction      = kI2C_Read;
+    masterXfer.flags          = kI2C_TransferDefaultFlag;
+
+    return I2C_MasterTransferBlocking(base, &masterXfer);
+}
+
+void BOARD_Accel_I2C_Init(void)
+{
+    BOARD_I2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
+{
+    uint8_t data = (uint8_t)txBuff;
+
+    return BOARD_I2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
+}
+
+status_t BOARD_Accel_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+    return BOARD_I2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
+}
+
+void BOARD_Codec_I2C_Init(void)
+{
+    BOARD_I2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Codec_I2C_Send(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
+{
+    return BOARD_I2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
+                          txBuffSize);
+}
+
+status_t BOARD_Codec_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+    return BOARD_I2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
+}
+#endif /* SDK_I2C_BASED_COMPONENT_USED */

example_code/i2c/read_accel_value_transfer/board.h

@@ -0,0 +1,230 @@
+/*
+ * Copyright 2017-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "clock_config.h"
+#include "fsl_common.h"
+#include "fsl_reset.h"
+#include "fsl_gpio.h"
+#include "fsl_iocon.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "LPCXpresso55S16"
+
+/*! @brief The UART to use for debug messages. */
+/* TODO: rename UART to USART */
+#define BOARD_DEBUG_UART_TYPE       kSerialPort_Uart
+#define BOARD_DEBUG_UART_BASEADDR   (uint32_t) USART0
+#define BOARD_DEBUG_UART_INSTANCE   0U
+#define BOARD_DEBUG_UART_CLK_FREQ   12000000U
+#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM0
+#define BOARD_DEBUG_UART_RST        kFC0_RST_SHIFT_RSTn
+#define BOARD_DEBUG_UART_CLKSRC     kCLOCK_Flexcomm0
+#define BOARD_UART_IRQ_HANDLER      FLEXCOMM0_IRQHandler
+#define BOARD_UART_IRQ              FLEXCOMM0_IRQn
+
+#define BOARD_ACCEL_I2C_BASEADDR   I2C4
+#define BOARD_ACCEL_I2C_CLOCK_FREQ 12000000
+
+#ifndef BOARD_DEBUG_UART_BAUDRATE
+#define BOARD_DEBUG_UART_BAUDRATE 115200U
+#endif /* BOARD_DEBUG_UART_BAUDRATE */
+
+#define BOARD_CODEC_I2C_BASEADDR   I2C4
+#define BOARD_CODEC_I2C_CLOCK_FREQ 12000000
+#define BOARD_CODEC_I2C_INSTANCE   4
+#ifndef BOARD_LED_RED_GPIO
+#define BOARD_LED_RED_GPIO GPIO
+#endif
+#define BOARD_LED_RED_GPIO_PORT 1U
+#ifndef BOARD_LED_RED_GPIO_PIN
+#define BOARD_LED_RED_GPIO_PIN 4U
+#endif
+
+#ifndef BOARD_LED_BLUE_GPIO
+#define BOARD_LED_BLUE_GPIO GPIO
+#endif
+#define BOARD_LED_BLUE_GPIO_PORT 1U
+#ifndef BOARD_LED_BLUE_GPIO_PIN
+#define BOARD_LED_BLUE_GPIO_PIN 6U
+#endif
+
+#ifndef BOARD_LED_GREEN_GPIO
+#define BOARD_LED_GREEN_GPIO GPIO
+#endif
+#define BOARD_LED_GREEN_GPIO_PORT 1U
+#ifndef BOARD_LED_GREEN_GPIO_PIN
+#define BOARD_LED_GREEN_GPIO_PIN 7U
+#endif
+
+#ifndef BOARD_SW1_GPIO
+#define BOARD_SW1_GPIO GPIO
+#endif
+#define BOARD_SW1_GPIO_PORT 1U
+#ifndef BOARD_SW1_GPIO_PIN
+#define BOARD_SW1_GPIO_PIN 18U
+#endif
+#define BOARD_SW1_NAME        "SW1"
+#define BOARD_SW1_IRQ         PIN_INT1_IRQn
+#define BOARD_SW1_IRQ_HANDLER PIN_INT1_IRQHandler
+
+#ifndef BOARD_SW3_GPIO
+#define BOARD_SW3_GPIO GPIO
+#endif
+#define BOARD_SW3_GPIO_PORT 1U
+#ifndef BOARD_SW3_GPIO_PIN
+#define BOARD_SW3_GPIO_PIN 9U
+#endif
+#define BOARD_SW3_NAME              "SW3"
+#define BOARD_SW3_IRQ               PIN_INT1_IRQn
+#define BOARD_SW3_IRQ_HANDLER       PIN_INT1_IRQHandler
+#define BOARD_SW3_GPIO_PININT_INDEX 1
+
+#ifndef BOARD_SW4_GPIO
+#define BOARD_SW4_GPIO GPIO
+#endif
+#define BOARD_SW4_GPIO_PORT 0U
+#ifndef BOARD_SW4_GPIO_PIN
+#define BOARD_SW4_GPIO_PIN 5U
+#endif
+#define BOARD_SW4_NAME              "SW4"
+#define BOARD_SW4_IRQ               PIN_INT0_IRQn
+#define BOARD_SW4_IRQ_HANDLER       PIN_INT0_IRQHandler
+#define BOARD_SW4_GPIO_PININT_INDEX 1
+
+/* USB PHY condfiguration */
+#define BOARD_USB_PHY_D_CAL     (0x05U)
+#define BOARD_USB_PHY_TXCAL45DP (0x0AU)
+#define BOARD_USB_PHY_TXCAL45DM (0x0AU)
+
+#define BOARD_SDIF_BASEADDR       SDIF
+#define BOARD_SDIF_CLKSRC         kCLOCK_SDio
+#define BOARD_SDIF_CLK_FREQ       CLOCK_GetSdioClkFreq()
+#define BOARD_SDIF_CLK_ATTACH     kMAIN_CLK_to_SDIO_CLK
+#define BOARD_SDIF_IRQ            SDIO_IRQn
+#define BOARD_MMC_VCC_SUPPLY      kMMC_VoltageWindows270to360
+#define BOARD_SD_CARD_DETECT_PIN  17
+#define BOARD_SD_CARD_DETECT_PORT 0
+#define BOARD_SD_CARD_DETECT_GPIO GPIO
+#define BOARD_SD_DETECT_TYPE      kSDMMCHOST_DetectCardByHostCD
+
+#define BOARD_SDIF_CD_GPIO_INIT()                                                                    \
+    {                                                                                                \
+        CLOCK_EnableClock(kCLOCK_Gpio2);                                                             \
+        GPIO_PinInit(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN, \
+                     &(gpio_pin_config_t){kGPIO_DigitalInput, 0U});                                  \
+    }
+#define BOARD_SDIF_CD_STATUS() \
+    GPIO_PinRead(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN)
+
+/* Board led color mapping */
+#define LOGIC_LED_ON  1U
+#define LOGIC_LED_OFF 0U
+
+#define BOARD_SDIF_CLK_ATTACH kMAIN_CLK_to_SDIO_CLK
+
+#define LED_RED_INIT(output)                                                                          \
+    {                                                                                                 \
+        IOCON_PinMuxSet(IOCON, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, IOCON_DIGITAL_EN);    \
+        GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN,             \
+                     &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \
+    }
+#define LED_RED_OFF()                                           \
+    GPIO_PortClear(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+                   1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED1 */
+#define LED_RED_ON()                                                                        \
+    GPIO_PortSet(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT,                               \
+                 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED1 \ \ \ \ \ \ \ \ \ \ \
+                                                */
+#define LED_RED_TOGGLE()                                         \
+    GPIO_PortToggle(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+                    1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED1 */
+
+#define LED_BLUE_INIT(output)                                                                         \
+    {                                                                                                 \
+        IOCON_PinMuxSet(IOCON, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, IOCON_DIGITAL_EN);  \
+        GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN,          \
+                     &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \
+    }
+#define LED_BLUE_OFF()                                            \
+    GPIO_PortClear(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                   1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED1 */
+#define LED_BLUE_ON()                                           \
+    GPIO_PortSet(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED1 */
+#define LED_BLUE_TOGGLE()                                          \
+    GPIO_PortToggle(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                    1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED1 */
+
+#define LED_GREEN_INIT(output)                                                              \
+    GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, BOARD_LED_GREEN_GPIO_PIN, \
+                 &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED1 */
+#define LED_GREEN_OFF()                                             \
+    GPIO_PortClear(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                   1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED1 */
+#define LED_GREEN_ON()                                            \
+    GPIO_PortSet(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED1 */
+#define LED_GREEN_TOGGLE()                                           \
+    GPIO_PortToggle(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                    1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED1 */
+
+/* Display. */
+#define BOARD_LCD_DC_GPIO      GPIO
+#define BOARD_LCD_DC_GPIO_PORT 1U
+#define BOARD_LCD_DC_GPIO_PIN  5U
+
+/* Serial MWM WIFI */
+#define BOARD_SERIAL_MWM_PORT_CLK_FREQ CLOCK_GetFlexCommClkFreq(2)
+#define BOARD_SERIAL_MWM_PORT          USART2
+#define BOARD_SERIAL_MWM_PORT_IRQn     FLEXCOMM2_IRQn
+#define BOARD_SERIAL_MWM_RST_WRITE(output)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz);
+status_t BOARD_I2C_Send(I2C_Type *base,
+                        uint8_t deviceAddress,
+                        uint32_t subAddress,
+                        uint8_t subaddressSize,
+                        uint8_t *txBuff,
+                        uint8_t txBuffSize);
+status_t BOARD_I2C_Receive(I2C_Type *base,
+                           uint8_t deviceAddress,
+                           uint32_t subAddress,
+                           uint8_t subaddressSize,
+                           uint8_t *rxBuff,
+                           uint8_t rxBuffSize);
+void BOARD_Accel_I2C_Init(void);
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
+status_t BOARD_Accel_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+void BOARD_Codec_I2C_Init(void);
+status_t BOARD_Codec_I2C_Send(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
+status_t BOARD_Codec_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */

example_code/i2c/read_accel_value_transfer/clock_config.c

@@ -0,0 +1,380 @@
+/*
+ * Copyright 2017-2018 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to set up clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up wait states of the flash.
+ *
+ * 3. Set up all dividers.
+ *
+ * 4. Set up all selectors to provide selected clocks.
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v7.0
+processor: LPC55S16
+package_id: LPC55S16JBD100
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+board: LPCXpresso55S16
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockPLL150M();
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 12 MHz}
+settings:
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    POWER_SetVoltageForFreq(12000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(12000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO12M */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF96M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF96M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    POWER_SetVoltageForFreq(96000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(96000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL100M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 100 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
+- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
+- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL100M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable High speed Crystal oscillator output to system  */
+
+    POWER_SetVoltageForFreq(100000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(100000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U),
+        .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
+        .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
+        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+        .pllRate = 100000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL150M
+called_from_default_init: true
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 150 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true}
+- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true}
+- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true}
+sources:
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL150M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable High speed Crystal oscillator output to system  */
+
+    POWER_SetVoltageForFreq(150000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(150000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
+        .pllndec = SYSCON_PLL0NDEC_NDIV(8U),
+        .pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
+        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+        .pllRate = 150000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockPLL1_150M ********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL1_150M
+outputs:
+- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 150 MHz}
+settings:
+- {id: PLL1_Mode, value: Normal}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS}
+- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL1M_MULT.scale, value: '150', locked: true}
+- {id: SYSCON.PLL1N_DIV.scale, value: '8', locked: true}
+- {id: SYSCON.PLL1_PDEC.scale, value: '2', locked: true}
+sources:
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL1_150M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable High speed Crystal oscillator output to system  */
+
+    POWER_SetVoltageForFreq(150000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(150000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL1 */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL1);                    /*!< Switch PLL1CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL1);                  /* Ensure PLL is on  */
+    const pll_setup_t pll1Setup = {
+        .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(53U) | SYSCON_PLL1CTRL_SELP(31U),
+        .pllndec = SYSCON_PLL1NDEC_NDIV(8U),
+        .pllpdec = SYSCON_PLL1PDEC_PDIV(1U),
+        .pllmdec = SYSCON_PLL1MDEC_MDIV(150U),
+        .pllRate = 150000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL1Freq(&pll1Setup);                        /*!< Configure PLL1 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL1_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL1 */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK;
+#endif
+}
+

example_code/i2c/read_accel_value_transfer/clock_config.h

@@ -0,0 +1,173 @@
+/*
+ * Copyright 2017-2018 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         16000000U  /*!< Board xtal frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK         96000000U  /*!< Core clock frequency: 96000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF96M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL100M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         150000000U  /*!< Core clock frequency: 150000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockPLL1_150M ********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK       150000000U  /*!< Core clock frequency: 150000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL1_150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL1_150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+

example_code/i2c/read_accel_value_transfer/i2c_read_accel_value_transfer.c

@@ -0,0 +1,457 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*  SDK Included Files */
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_debug_console.h"
+#include "fsl_i2c.h"
+
+#include "fsl_gpio.h"
+#include "fsl_power.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define ACCEL_I2C_CLK_SRC     I2C4_BASE
+#define ACCEL_I2C_CLK_FREQ    12000000
+#define I2C_BAUDRATE          100000
+#define I2C_RELEASE_BUS_COUNT 100U
+/* MMA8491 does not have WHO_AM_I, DATA_CFG amd CTRL registers */
+#if !(defined(I2C_ACCEL_MMA8491) && I2C_ACCEL_MMA8491)
+#define FXOS8700_WHOAMI    0xC7U
+#define MMA8451_WHOAMI     0x1AU
+#define MMA8652_WHOAMI     0x4AU
+#define ACCEL_XYZ_DATA_CFG 0x0EU
+#define ACCEL_CTRL_REG1    0x2AU
+/* FXOS8700 and MMA8451 have the same who_am_i register address. */
+#define ACCEL_WHOAMI_REG 0x0DU
+#endif
+#define ACCEL_STATUS     0x00U
+#define ACCEL_READ_TIMES 10U
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+void BOARD_I2C_ReleaseBus(void);
+#if !(defined(I2C_ACCEL_MMA8491) && I2C_ACCEL_MMA8491)
+static bool I2C_ReadAccelWhoAmI(void);
+static bool I2C_WriteAccelReg(I2C_Type *base, uint8_t device_addr, uint8_t reg_addr, uint8_t value);
+#endif
+static bool I2C_ReadAccelRegs(I2C_Type *base, uint8_t device_addr, uint8_t reg_addr, uint8_t *rxBuff, uint32_t rxSize);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+uint8_t MSBshift = 8U;
+uint8_t LSBshift = 2U;
+#if defined(I2C_ACCEL_MMA8491) && I2C_ACCEL_MMA8491
+uint8_t g_mma8491_addr = 0x55U;
+#else
+/* FXOS8700, MMA8652 and MMA8451 device address */
+const uint8_t g_accel_address[] = {0x1CU, 0x1DU, 0x1EU, 0x1FU};
+#endif
+uint8_t g_accel_addr_found = 0x00;
+i2c_master_handle_t g_m_handle;
+
+volatile bool completionFlag = false;
+volatile bool nakFlag        = false;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static void i2c_release_bus_delay(void)
+{
+    uint32_t i = 0;
+    for (i = 0; i < I2C_RELEASE_BUS_COUNT; i++)
+    {
+        __NOP();
+    }
+}
+
+void BOARD_I2C_ReleaseBus(void)
+{
+    uint8_t i = 0;
+
+    IOCON->PIO[1][20] &= 0xFFF1;
+    IOCON->PIO[1][21] &= 0xFFF1;
+
+    /* Drive SDA low first to simulate a start */
+    GPIO_PinWrite(GPIO, 1U, 21U, 0U);
+    i2c_release_bus_delay();
+
+    /* Send 9 pulses on SCL and keep SDA high */
+    for (i = 0; i < 9; i++)
+    {
+        GPIO_PinWrite(GPIO, 1U, 20U, 0U);
+        i2c_release_bus_delay();
+
+        GPIO_PinWrite(GPIO, 1U, 21U, 1U);
+        i2c_release_bus_delay();
+
+        GPIO_PinWrite(GPIO, 1U, 20U, 1U);
+        i2c_release_bus_delay();
+        i2c_release_bus_delay();
+    }
+
+    /* Send stop */
+    GPIO_PinWrite(GPIO, 1U, 20U, 0U);
+    i2c_release_bus_delay();
+
+    GPIO_PinWrite(GPIO, 1U, 21U, 0U);
+    i2c_release_bus_delay();
+
+    GPIO_PinWrite(GPIO, 1U, 20U, 1U);
+    i2c_release_bus_delay();
+
+    GPIO_PinWrite(GPIO, 1U, 21U, 1U);
+    i2c_release_bus_delay();
+}
+
+static void i2c_master_callback(I2C_Type *base, i2c_master_handle_t *handle, status_t status, void *userData)
+{
+    /* Signal transfer success when received success status. */
+    if (status == kStatus_Success)
+    {
+        completionFlag = true;
+    }
+    /* Signal transfer success when received success status. */
+    if ((status == kStatus_I2C_Nak) || (status == kStatus_I2C_Addr_Nak))
+    {
+        nakFlag = true;
+    }
+}
+
+static void I2C_InitModule(void)
+{
+    i2c_master_config_t masterConfig;
+    uint32_t sourceClock = 0;
+
+    /*
+     * masterConfig.baudRate_Bps = 100000U;
+     * masterConfig.enableStopHold = false;
+     * masterConfig.glitchFilterWidth = 0U;
+     * masterConfig.enableMaster = true;
+     */
+    I2C_MasterGetDefaultConfig(&masterConfig);
+    masterConfig.baudRate_Bps = I2C_BAUDRATE;
+    sourceClock               = ACCEL_I2C_CLK_FREQ;
+    I2C_MasterInit(BOARD_ACCEL_I2C_BASEADDR, &masterConfig, sourceClock);
+}
+
+#if !(defined(I2C_ACCEL_MMA8491) && I2C_ACCEL_MMA8491)
+static bool I2C_ReadAccelWhoAmI(void)
+{
+    /*
+    How to read the device who_am_I value ?
+    Start + Device_address_Write , who_am_I_register;
+    Repeart_Start + Device_address_Read , who_am_I_value.
+    */
+    uint8_t who_am_i_reg          = ACCEL_WHOAMI_REG;
+    uint8_t who_am_i_value        = 0x00;
+    uint8_t accel_addr_array_size = 0x00;
+    bool find_device              = false;
+    uint8_t i                     = 0;
+
+    I2C_InitModule();
+
+    i2c_master_transfer_t masterXfer;
+    memset(&masterXfer, 0, sizeof(masterXfer));
+
+    masterXfer.slaveAddress   = g_accel_address[0];
+    masterXfer.direction      = kI2C_Write;
+    masterXfer.subaddress     = 0;
+    masterXfer.subaddressSize = 0;
+    masterXfer.data           = &who_am_i_reg;
+    masterXfer.dataSize       = 1;
+    masterXfer.flags          = kI2C_TransferNoStopFlag;
+
+    accel_addr_array_size = sizeof(g_accel_address) / sizeof(g_accel_address[0]);
+
+    for (i = 0; i < accel_addr_array_size; i++)
+    {
+        masterXfer.slaveAddress = g_accel_address[i];
+
+        I2C_MasterTransferNonBlocking(BOARD_ACCEL_I2C_BASEADDR, &g_m_handle, &masterXfer);
+
+        /*  wait for transfer completed. */
+        while ((!nakFlag) && (!completionFlag))
+        {
+        }
+
+        nakFlag = false;
+
+        if (completionFlag == true)
+        {
+            completionFlag     = false;
+            find_device        = true;
+            g_accel_addr_found = masterXfer.slaveAddress;
+            break;
+        }
+    }
+
+    if (find_device == true)
+    {
+        masterXfer.direction      = kI2C_Read;
+        masterXfer.subaddress     = 0;
+        masterXfer.subaddressSize = 0;
+        masterXfer.data           = &who_am_i_value;
+        masterXfer.dataSize       = 1;
+        masterXfer.flags          = kI2C_TransferRepeatedStartFlag;
+
+        I2C_MasterTransferNonBlocking(BOARD_ACCEL_I2C_BASEADDR, &g_m_handle, &masterXfer);
+
+        /*  wait for transfer completed. */
+        while ((!nakFlag) && (!completionFlag))
+        {
+        }
+
+        nakFlag = false;
+
+        if (completionFlag == true)
+        {
+            completionFlag = false;
+            if (who_am_i_value == FXOS8700_WHOAMI)
+            {
+                PRINTF("Found an FXOS8700 on board , the device address is 0x%x . \r\n", masterXfer.slaveAddress);
+                return true;
+            }
+            else if (who_am_i_value == MMA8451_WHOAMI)
+            {
+                PRINTF("Found an MMA8451 on board , the device address is 0x%x . \r\n", masterXfer.slaveAddress);
+                return true;
+            }
+            else if (who_am_i_value == MMA8652_WHOAMI)
+            {
+                LSBshift = 4U;
+                PRINTF("Found an MMA8652 on board , the device address is 0x%x . \r\n", masterXfer.slaveAddress);
+                return true;
+            }
+            else
+            {
+                PRINTF("Found a device, the WhoAmI value is 0x%x\r\n", who_am_i_value);
+                PRINTF("It's not MMA8451 or FXOS8700 or MMA8652. \r\n");
+                PRINTF("The device address is 0x%x. \r\n", masterXfer.slaveAddress);
+                return false;
+            }
+        }
+        else
+        {
+            PRINTF("Not a successful i2c communication \r\n");
+            return false;
+        }
+    }
+    else
+    {
+        PRINTF("\r\n Do not find an accelerometer device ! \r\n");
+        return false;
+    }
+}
+
+static bool I2C_WriteAccelReg(I2C_Type *base, uint8_t device_addr, uint8_t reg_addr, uint8_t value)
+{
+    i2c_master_transfer_t masterXfer;
+    memset(&masterXfer, 0, sizeof(masterXfer));
+
+    masterXfer.slaveAddress   = device_addr;
+    masterXfer.direction      = kI2C_Write;
+    masterXfer.subaddress     = reg_addr;
+    masterXfer.subaddressSize = 1;
+    masterXfer.data           = &value;
+    masterXfer.dataSize       = 1;
+    masterXfer.flags          = kI2C_TransferDefaultFlag;
+
+    /*  direction=write : start+device_write;cmdbuff;xBuff; */
+    /*  direction=recive : start+device_write;cmdbuff;repeatStart+device_read;xBuff; */
+
+    I2C_MasterTransferNonBlocking(BOARD_ACCEL_I2C_BASEADDR, &g_m_handle, &masterXfer);
+
+    /*  wait for transfer completed. */
+    while ((!nakFlag) && (!completionFlag))
+    {
+    }
+
+    nakFlag = false;
+
+    if (completionFlag == true)
+    {
+        completionFlag = false;
+        return true;
+    }
+    else
+    {
+        return false;
+    }
+}
+#endif
+
+static bool I2C_ReadAccelRegs(I2C_Type *base, uint8_t device_addr, uint8_t reg_addr, uint8_t *rxBuff, uint32_t rxSize)
+{
+    i2c_master_transfer_t masterXfer;
+    memset(&masterXfer, 0, sizeof(masterXfer));
+    masterXfer.slaveAddress   = device_addr;
+    masterXfer.direction      = kI2C_Read;
+    masterXfer.subaddress     = reg_addr;
+    masterXfer.subaddressSize = 1;
+    masterXfer.data           = rxBuff;
+    masterXfer.dataSize       = rxSize;
+    masterXfer.flags          = kI2C_TransferDefaultFlag;
+
+    /*  direction=write : start+device_write;cmdbuff;xBuff; */
+    /*  direction=recive : start+device_write;cmdbuff;repeatStart+device_read;xBuff; */
+
+    I2C_MasterTransferNonBlocking(BOARD_ACCEL_I2C_BASEADDR, &g_m_handle, &masterXfer);
+
+    /*  wait for transfer completed. */
+    while ((!nakFlag) && (!completionFlag))
+    {
+    }
+
+    nakFlag = false;
+
+    if (completionFlag == true)
+    {
+        completionFlag = false;
+        return true;
+    }
+    else
+    {
+        return false;
+    }
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+    bool isThereAccel = false;
+    /* set BOD VBAT level to 1.65V */
+    POWER_SetBodVbatLevel(kPOWER_BodVbatLevel1650mv, kPOWER_BodHystLevel50mv, false);
+    /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
+    CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+
+    /* attach 12 MHz clock to FLEXCOMM4 (I2C master) */
+    CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
+
+    /* reset FLEXCOMM for I2C */
+    RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn);
+
+    BOARD_InitBootPins();
+    BOARD_InitBootClocks();
+    //   BOARD_I2C_ReleaseBus();
+    BOARD_InitDebugConsole();
+
+    PRINTF("\r\nI2C example -- Read Accelerometer Value\r\n");
+
+    I2C_MasterTransferCreateHandle(BOARD_ACCEL_I2C_BASEADDR, &g_m_handle, i2c_master_callback, NULL);
+#if defined(I2C_ACCEL_MMA8491) && I2C_ACCEL_MMA8491
+    uint8_t status0_value                = 0;
+    gpio_pin_config_t tilt_enable_config = {.pinDirection = kGPIO_DigitalOutput, .outputLogic = 0U};
+
+    /* Enable sensor */
+    GPIO_PinInit(BOARD_TILT_ENABLE_GPIO, BOARD_TILT_ENABLE_GPIO_PIN, &tilt_enable_config);
+
+    I2C_InitModule();
+
+    /* If using MMA8491, then perform get status operation to g_mma8491_addr to check whether it is welded on board. */
+    isThereAccel = I2C_ReadAccelRegs(BOARD_ACCEL_I2C_BASEADDR, g_mma8491_addr, ACCEL_STATUS, &status0_value, 1);
+    if (isThereAccel)
+    {
+        PRINTF("Found MMA8491 on board, the device address is 0x%x. \r\n", g_mma8491_addr);
+        g_accel_addr_found = g_mma8491_addr;
+    }
+    else
+    {
+        PRINTF("\r\nDo not find an accelerometer device ! \r\n");
+    }
+#else
+    /* For other sensors, check the type of the sensor */
+    isThereAccel = I2C_ReadAccelWhoAmI();
+#endif
+
+    /*  read the accel xyz value if there is accel device on board */
+    if (true == isThereAccel)
+    {
+        uint32_t i = 0U;
+        uint8_t readBuff[7];
+        int16_t x, y, z;
+#if !(defined(I2C_ACCEL_MMA8491) && I2C_ACCEL_MMA8491)
+        uint8_t databyte  = 0;
+        uint8_t write_reg = 0;
+
+        /*  please refer to the "example FXOS8700CQ Driver Code" in FXOS8700 datasheet. */
+        /*  write 0000 0000 = 0x00 to accelerometer control register 1 */
+        /*  standby */
+        /*  [7-1] = 0000 000 */
+        /*  [0]: active=0 */
+        write_reg = ACCEL_CTRL_REG1;
+        databyte  = 0;
+        I2C_WriteAccelReg(BOARD_ACCEL_I2C_BASEADDR, g_accel_addr_found, write_reg, databyte);
+
+        /*  write 0000 0001= 0x01 to XYZ_DATA_CFG register */
+        /*  [7]: reserved */
+        /*  [6]: reserved */
+        /*  [5]: reserved */
+        /*  [4]: hpf_out=0 */
+        /*  [3]: reserved */
+        /*  [2]: reserved */
+        /*  [1-0]: fs=01 for accelerometer range of +/-4g range with 0.488mg/LSB */
+        /*  databyte = 0x01; */
+        write_reg = ACCEL_XYZ_DATA_CFG;
+        databyte  = 0x01;
+        I2C_WriteAccelReg(BOARD_ACCEL_I2C_BASEADDR, g_accel_addr_found, write_reg, databyte);
+
+        /*  write 0000 1101 = 0x0D to accelerometer control register 1 */
+        /*  [7-6]: aslp_rate=00 */
+        /*  [5-3]: dr=001 for 200Hz data rate (when in hybrid mode) */
+        /*  [2]: lnoise=1 for low noise mode */
+        /*  [1]: f_read=0 for normal 16 bit reads */
+        /*  [0]: active=1 to take the part out of standby and enable sampling */
+        /*   databyte = 0x0D; */
+        write_reg = ACCEL_CTRL_REG1;
+        databyte  = 0x0d;
+        I2C_WriteAccelReg(BOARD_ACCEL_I2C_BASEADDR, g_accel_addr_found, write_reg, databyte);
+#endif
+        PRINTF("The accel values:\r\n");
+        for (i = 0; i < ACCEL_READ_TIMES; i++)
+        {
+            /*  wait for new data are ready. */
+#if defined(I2C_ACCEL_MMA8491) && I2C_ACCEL_MMA8491
+            /* Disable and re-enable sensor to get another reading */
+            GPIO_PortToggle(BOARD_TILT_ENABLE_GPIO, 1U << BOARD_TILT_ENABLE_GPIO_PIN);
+            GPIO_PortToggle(BOARD_TILT_ENABLE_GPIO, 1U << BOARD_TILT_ENABLE_GPIO_PIN);
+            status0_value = 0;
+            while (status0_value != 0xfU)
+#else
+            uint8_t status0_value = 0;
+            while (status0_value != 0xffU)
+#endif
+            {
+                I2C_ReadAccelRegs(BOARD_ACCEL_I2C_BASEADDR, g_accel_addr_found, ACCEL_STATUS, &status0_value, 1);
+            }
+
+            /*  Multiple-byte Read from STATUS (0x00) register */
+            I2C_ReadAccelRegs(BOARD_ACCEL_I2C_BASEADDR, g_accel_addr_found, ACCEL_STATUS, readBuff, 7);
+
+            status0_value = readBuff[0];
+            x             = ((int16_t)(((readBuff[1] << MSBshift) | readBuff[2]))) >> LSBshift;
+            y             = ((int16_t)(((readBuff[3] << MSBshift) | readBuff[4]))) >> LSBshift;
+            z             = ((int16_t)(((readBuff[5] << MSBshift) | readBuff[6]))) >> LSBshift;
+
+            PRINTF("status_reg = 0x%x , x = %5d , y = %5d , z = %5d \r\n", status0_value, x, y, z);
+        }
+    }
+
+    PRINTF("\r\nEnd of I2C example .\r\n");
+    while (1)
+    {
+    }
+}

example_code/i2c/read_accel_value_transfer/i2c_read_accel_value_transfer_v3_9.xml

@@ -0,0 +1,125 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<ksdk:examples xmlns:ksdk="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd manifest.xsd">
+  <externalDefinitions>
+    <definition extID="utility.debug_console_lite.LPC55S16"/>
+    <definition extID="platform.utilities.assert_lite.LPC55S16"/>
+    <definition extID="platform.drivers.flexcomm_i2c.LPC55S16"/>
+    <definition extID="platform.drivers.common.LPC55S16"/>
+    <definition extID="platform.drivers.power.LPC55S16"/>
+    <definition extID="platform.drivers.lpc_iocon.LPC55S16"/>
+    <definition extID="platform.drivers.lpc_gpio.LPC55S16"/>
+    <definition extID="platform.drivers.inputmux.LPC55S16"/>
+    <definition extID="platform.drivers.clock.LPC55S16"/>
+    <definition extID="device.LPC55S16_CMSIS.LPC55S16"/>
+    <definition extID="device.LPC55S16_startup.LPC55S16"/>
+    <definition extID="platform.drivers.flexcomm_usart.LPC55S16"/>
+    <definition extID="platform.drivers.flexcomm.LPC55S16"/>
+    <definition extID="component.usart_adapter.LPC55S16"/>
+    <definition extID="component.lists.LPC55S16"/>
+    <definition extID="platform.drivers.reset.LPC55S16"/>
+    <definition extID="CMSIS_Include_core_cm.LPC55S16"/>
+    <definition extID="platform.drivers.inputmux_connections.LPC55S16"/>
+    <definition extID="platform.utilities.misc_utilities.LPC55S16"/>
+    <definition extID="device.LPC55S16_system.LPC55S16"/>
+    <definition extID="iar"/>
+    <definition extID="mdk"/>
+    <definition extID="armgcc"/>
+    <definition extID="mcuxpresso"/>
+    <definition extID="com.nxp.mcuxpresso"/>
+  </externalDefinitions>
+  <example id="lpcxpresso55s16_i2c_read_accel_value_transfer" name="i2c_read_accel_value_transfer" dependency="utility.debug_console_lite.LPC55S16 platform.utilities.assert_lite.LPC55S16 platform.drivers.flexcomm_i2c.LPC55S16 platform.drivers.common.LPC55S16 platform.drivers.power.LPC55S16 platform.drivers.lpc_iocon.LPC55S16 platform.drivers.lpc_gpio.LPC55S16 platform.drivers.inputmux.LPC55S16 platform.drivers.clock.LPC55S16 device.LPC55S16_CMSIS.LPC55S16 device.LPC55S16_startup.LPC55S16 platform.drivers.flexcomm_usart.LPC55S16 platform.drivers.flexcomm.LPC55S16 component.usart_adapter.LPC55S16 component.lists.LPC55S16 platform.drivers.reset.LPC55S16 CMSIS_Include_core_cm.LPC55S16 platform.drivers.inputmux_connections.LPC55S16 platform.utilities.misc_utilities.LPC55S16 device.LPC55S16_system.LPC55S16" category="driver_examples/i2c">
+    <projects>
+      <project type="com.crt.advproject.projecttype.exe" nature="org.eclipse.cdt.core.cnature"/>
+    </projects>
+    <toolchainSettings>
+      <toolchainSetting id_refs="com.nxp.mcuxpresso">
+        <option id="gnu.c.compiler.option.preprocessor.def.symbols" type="stringList">
+          <value>CPU_LPC55S16JBD100</value>
+          <value>PRINTF_ADVANCED_ENABLE=1</value>
+          <value>MCUXPRESSO_SDK</value>
+        </option>
+        <option id="com.crt.advproject.gas.fpu" type="enum">
+          <value>com.crt.advproject.gas.fpu.fpv5sp.hard</value>
+        </option>
+        <option id="com.crt.advproject.gcc.fpu" type="enum">
+          <value>com.crt.advproject.gcc.fpu.fpv5sp.hard</value>
+        </option>
+        <option id="gnu.c.compiler.option.optimization.flags" type="string">
+          <value>-fno-common</value>
+        </option>
+        <option id="com.crt.advproject.c.misc.dialect" type="enum">
+          <value>com.crt.advproject.misc.dialect.gnu99</value>
+        </option>
+        <option id="gnu.c.compiler.option.misc.other" type="string">
+          <value>-mcpu=cortex-m33 -c -ffunction-sections -fdata-sections -ffreestanding -fno-builtin</value>
+        </option>
+        <option id="gnu.c.compiler.option.warnings.allwarn" type="boolean">
+          <value>false</value>
+        </option>
+        <option id="com.crt.advproject.link.fpu" type="enum">
+          <value>com.crt.advproject.link.fpu.fpv5sp.hard</value>
+        </option>
+        <option id="gnu.c.link.option.nostdlibs" type="boolean">
+          <value>true</value>
+        </option>
+      </toolchainSetting>
+    </toolchainSettings>
+    <include_paths>
+      <include_path path="boards/lpcxpresso55s16/driver_examples/i2c/read_accel_value_transfer" project_relative_path="board" type="c_include"/>
+    </include_paths>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/read_accel_value_transfer/iar" project_relative_path="./" type="workspace" toolchain="iar">
+      <files mask="i2c_read_accel_value_transfer.ewd"/>
+      <files mask="i2c_read_accel_value_transfer.ewp"/>
+      <files mask="i2c_read_accel_value_transfer.eww"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/read_accel_value_transfer/mdk" project_relative_path="./" type="workspace" toolchain="mdk">
+      <files mask="i2c_read_accel_value_transfer.uvprojx"/>
+      <files mask="i2c_read_accel_value_transfer.uvoptx"/>
+      <files mask="JLinkSettings.JLinkScript"/>
+      <files mask="JLinkSettings.ini"/>
+      <files mask="i2c_read_accel_value_transfer.uvmpw"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/read_accel_value_transfer/armgcc" project_relative_path="./" type="workspace" toolchain="armgcc">
+      <files mask="build_all.bat"/>
+      <files mask="build_all.sh"/>
+      <files mask="clean.bat"/>
+      <files mask="clean.sh"/>
+      <files mask="CMakeLists.txt"/>
+      <files mask="flags.cmake"/>
+      <files mask="config.cmake"/>
+      <files mask="build_debug.bat"/>
+      <files mask="build_debug.sh"/>
+      <files mask="build_release.bat"/>
+      <files mask="build_release.sh"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/read_accel_value_transfer" project_relative_path="source" type="src">
+      <files mask="i2c_read_accel_value_transfer.c"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/read_accel_value_transfer" project_relative_path="board" type="src">
+      <files mask="pin_mux.c"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/read_accel_value_transfer" project_relative_path="board" type="c_include">
+      <files mask="pin_mux.h"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/read_accel_value_transfer" project_relative_path="board" type="src">
+      <files mask="board.c"/>
+      <files mask="clock_config.c"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/read_accel_value_transfer" project_relative_path="board" type="c_include">
+      <files mask="board.h"/>
+      <files mask="clock_config.h"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/read_accel_value_transfer" project_relative_path="doc" type="doc" toolchain="iar mdk mcuxpresso armgcc">
+      <files mask="readme.txt"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/read_accel_value_transfer/iar" project_relative_path="LPC55S16/iar" type="linker" toolchain="iar">
+      <files mask="LPC55S16_flash.icf"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/read_accel_value_transfer/mdk" project_relative_path="LPC55S16/arm" type="linker" toolchain="mdk">
+      <files mask="LPC55S16_flash.scf"/>
+    </source>
+    <source path="boards/lpcxpresso55s16/driver_examples/i2c/read_accel_value_transfer/armgcc" project_relative_path="LPC55S16/gcc" type="linker" toolchain="armgcc">
+      <files mask="LPC55S16_flash.ld"/>
+    </source>
+  </example>
+</ksdk:examples>

example_code/i2c/read_accel_value_transfer/pin_mux.c

@@ -0,0 +1,133 @@
+/*
+ * Copyright 2017-2020 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: LPC55S16
+package_id: LPC55S16JBD100
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_iocon.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29,
+    mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: inactive, slew_rate: standard,
+    invert: disabled, open_drain: disabled}
+  - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: inactive,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 */
+void BOARD_InitPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    const uint32_t port0_pin29_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
+                                         IOCON_PIO_FUNC1 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, 0U, 29U, port0_pin29_config);
+
+    const uint32_t port0_pin30_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
+                                         IOCON_PIO_FUNC1 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, 0U, 30U, port0_pin30_config);
+
+    const uint32_t port1_pin20_config = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */
+                                         IOCON_PIO_FUNC5 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, 1U, 20U, port1_pin20_config);
+
+    const uint32_t port1_pin21_config = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */
+                                         IOCON_PIO_FUNC5 |
+                                         /* No addition pin function */
+                                         IOCON_PIO_MODE_INACT |
+                                         /* Standard mode, output slew rate control is enabled */
+                                         IOCON_PIO_SLEW_STANDARD |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, 1U, 21U, port1_pin21_config);
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/

example_code/i2c/read_accel_value_transfer/pin_mux.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright 2017-2020 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC1 0x01u         /*!<@brief Selects pin function 1 */
+#define IOCON_PIO_FUNC5 0x05u         /*!<@brief Selects pin function 5 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u    /*!<@brief No addition pin function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/

example_code/i2c/read_accel_value_transfer/readme.txt

@@ -0,0 +1,61 @@
+Overview
+========
+The i2c_read_accel_value example shows how to use I2C driver to communicate with an i2c device:
+
+ 1. How to use the i2c driver to read a i2c device who_am_I register.
+ 2. How to use the i2c driver to write/read the device registers.
+
+In this example, the values of three-axis accelerometer print to the serial terminal on PC through
+the virtual serial port on board.
+
+Toolchain supported
+===================
+- IAR embedded Workbench  9.10.2
+- Keil MDK  5.34
+- GCC ARM Embedded  10.2.1
+- MCUXpresso  11.5.0
+
+Hardware requirements
+=====================
+- Mini/Micro USB cable
+- LPCXpresso55S16 boards
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+The jumper setting:
+    Default jumpers configuration does not work,  you will need to add JP20 and JP21 (JP22 optional for ADC use)
+
+# Prepare the Demo
+
+1. Connect a micro USB cable between the PC host and the LPC-Link USB port (J1) on the board.
+2. Open a serial terminal on PC for JLink serial device with these settings:
+   - 115200 baud rate
+   - 8 data bits
+   - No parity
+   - One stop bit
+   - No flow control
+3. Download the program to the target board.
+4. Either press the reset button on your board or launch the debugger in your IDE to begin running
+   the demo.
+
+Running the demo
+================
+When the example runs successfully, you can see the similar information from the terminal as below.
+
+I2C example -- Read Accelerometer Value
+Found an MMA8652 on board , the device address is 0x1d . 
+The accel values:
+status_reg = 0xff , x =  -192 , y =   188 , z =  2152 
+status_reg = 0xff , x =  -168 , y =   192 , z =  2160 
+status_reg = 0xff , x =  -180 , y =   152 , z =  2144 
+status_reg = 0xff , x =  -200 , y =   132 , z =  2064 
+status_reg = 0xff , x =  -192 , y =   108 , z =  2196 
+status_reg = 0xff , x =  -232 , y =   136 , z =  2092 
+status_reg = 0xff , x =  -260 , y =   192 , z =  1992 
+status_reg = 0xff , x =  -240 , y =   304 , z =  1968 
+status_reg = 0xff , x =  -208 , y =   336 , z =  1976 
+status_reg = 0xff , x =  -208 , y =   296 , z =  1900 
+
+End of I2C example .