256 lines
11 KiB
C
256 lines
11 KiB
C
/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016, NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_RESET_H_
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#define _FSL_RESET_H_
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#include <assert.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <string.h>
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#include "fsl_device_registers.h"
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/*!
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* @addtogroup reset
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! @brief reset driver version 2.0.0. */
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#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
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/*@}*/
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/*!
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* @brief Enumeration for peripheral reset control bits
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*
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* Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
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*/
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typedef enum _SYSCON_RSTn
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{
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kROM_RST_SHIFT_RSTn = 0 | 1U, /**< ROM reset control */
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kSRAM1_RST_SHIFT_RSTn = 0 | 3U, /**< SRAM1 reset control */
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kSRAM2_RST_SHIFT_RSTn = 0 | 4U, /**< SRAM2 reset control */
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kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */
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kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */
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kMUX0_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux0 reset control */
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kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */
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kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */
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kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */
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kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */
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kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */
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kDMA0_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */
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kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */
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kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */
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kRTC_RST_SHIFT_RSTn = 0 | 23U, /**< RTC reset control */
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kMAILBOX_RST_SHIFT_RSTn = 0 | 26U, /**< Mailbox reset control */
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kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */
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kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */
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kOSTIMER0_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer0 reset control */
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kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */
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kMCAN_RST_SHIFT_RSTn = 65536 | 7U, /**< MCAN reset control */
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kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */
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kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */
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kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */
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kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */
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kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */
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kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */
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kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */
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kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */
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kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */
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kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */
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kUSB0D_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0 Device reset control */
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kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */
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kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */
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kEZHA_RST_SHIFT_RSTn = 65536 | 30U, /**< EZHA reset control */
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kEZHB_RST_SHIFT_RSTn = 65536 | 31U, /**< EZHB reset control */
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kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */
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kCMP_RST_SHIFT_RSTn = 131072 | 2U, /**< CMP reset control */
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kUSB1H_RST_SHIFT_RSTn = 131072 | 4U, /**< USBHS Host reset control */
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kUSB1D_RST_SHIFT_RSTn = 131072 | 5U, /**< USBHS Device reset control */
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kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U, /**< USB RAM reset control */
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kUSB1_RST_SHIFT_RSTn = 131072 | 7U, /**< USBHS reset control */
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kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */
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kCDOG_RST_SHIFT_RSTn = 131072 | 11U, /**< Code Watchdog reset control */
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kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */
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kSYSCTL_RST_SHIFT_RSTn = 131072 | 15U, /**< SYSCTL reset control */
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kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U, /**< USB0HMR reset control */
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kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U, /**< USB0HSL reset control */
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kHASHCRYPT_RST_SHIFT_RSTn = 131072 | 18U, /**< HASHCRYPT reset control */
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kPLULUT_RST_SHIFT_RSTn = 131072 | 20U, /**< PLU LUT reset control */
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kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */
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kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */
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kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */
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kCASPER_RST_SHIFT_RSTn = 131072 | 24U, /**< CASPER reset control */
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kANALOGCTL_RST_SHIFT_RSTn = 131072 | 27U, /**< ANALOG_CTL reset control */
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kHSLSPI_RST_SHIFT_RSTn = 131072 | 28U, /**< HS LSPI reset control */
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kGPIOSEC_RST_SHIFT_RSTn = 131072 | 29U, /**< GPIO Secure reset control */
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kGPIOSECINT_RST_SHIFT_RSTn = 131072 | 30U, /**< GPIO Secure int reset control */
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} SYSCON_RSTn_t;
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/** Array initializers with peripheral reset bits **/
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#define ADC_RSTS \
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{ \
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kADC0_RST_SHIFT_RSTn \
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} /* Reset bits for ADC peripheral */
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#define MCAN_RSTS \
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{ \
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kMCAN_RST_SHIFT_RSTn \
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} /* Reset bits for CAN peripheral */
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#define CRC_RSTS \
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{ \
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kCRC_RST_SHIFT_RSTn \
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} /* Reset bits for CRC peripheral */
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#define CTIMER_RSTS \
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{ \
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kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \
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kCTIMER4_RST_SHIFT_RSTn \
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} /* Reset bits for CTIMER peripheral */
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#define DMA_RSTS_N \
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{ \
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kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \
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} /* Reset bits for DMA peripheral */
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#define FLEXCOMM_RSTS \
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{ \
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kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \
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kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kHSLSPI_RST_SHIFT_RSTn \
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} /* Reset bits for FLEXCOMM peripheral */
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#define GINT_RSTS \
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{ \
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kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \
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} /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */
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#define GPIO_RSTS_N \
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{ \
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kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn \
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} /* Reset bits for GPIO peripheral */
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#define INPUTMUX_RSTS \
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{ \
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kMUX0_RST_SHIFT_RSTn \
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} /* Reset bits for INPUTMUX peripheral */
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#define IOCON_RSTS \
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{ \
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kIOCON_RST_SHIFT_RSTn \
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} /* Reset bits for IOCON peripheral */
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#define FLASH_RSTS \
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{ \
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kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \
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} /* Reset bits for Flash peripheral */
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#define MRT_RSTS \
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{ \
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kMRT_RST_SHIFT_RSTn \
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} /* Reset bits for MRT peripheral */
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#define PINT_RSTS \
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{ \
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kPINT_RST_SHIFT_RSTn \
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} /* Reset bits for PINT peripheral */
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#define CDOG_RSTS \
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{ \
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kCDOG_RST_SHIFT_RSTn \
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} /* Reset bits for CDOG peripheral */
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#define RNG_RSTS \
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{ \
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kRNG_RST_SHIFT_RSTn \
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} /* Reset bits for RNG peripheral */
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#define SCT_RSTS \
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{ \
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kSCT0_RST_SHIFT_RSTn \
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} /* Reset bits for SCT peripheral */
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#define USB0D_RST \
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{ \
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kUSB0D_RST_SHIFT_RSTn \
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} /* Reset bits for USB0D peripheral */
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#define USB0HMR_RST \
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{ \
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kUSB0HMR_RST_SHIFT_RSTn \
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} /* Reset bits for USB0HMR peripheral */
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#define USB0HSL_RST \
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{ \
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kUSB0HSL_RST_SHIFT_RSTn \
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} /* Reset bits for USB0HSL peripheral */
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#define USB1H_RST \
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{ \
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kUSB1H_RST_SHIFT_RSTn \
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} /* Reset bits for USB1H peripheral */
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#define USB1D_RST \
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{ \
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kUSB1D_RST_SHIFT_RSTn \
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} /* Reset bits for USB1D peripheral */
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#define USB1RAM_RST \
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{ \
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kUSB1RAM_RST_SHIFT_RSTn \
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} /* Reset bits for USB1RAM peripheral */
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#define UTICK_RSTS \
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{ \
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kUTICK_RST_SHIFT_RSTn \
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} /* Reset bits for UTICK peripheral */
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#define WWDT_RSTS \
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{ \
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kWWDT_RST_SHIFT_RSTn \
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} /* Reset bits for WWDT peripheral */
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#define PLU_RSTS_N \
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{ \
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kPLULUT_RST_SHIFT_RSTn \
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} /* Reset bits for PLU peripheral */
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#define OSTIMER_RSTS \
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{ \
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kOSTIMER0_RST_SHIFT_RSTn \
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} /* Reset bits for OSTIMER peripheral */
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typedef SYSCON_RSTn_t reset_ip_name_t;
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*!
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* @brief Assert reset to peripheral.
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*
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* Asserts reset signal to specified peripheral module.
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*
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* @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
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* and reset bit position in the reset register.
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*/
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void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
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/*!
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* @brief Clear reset to peripheral.
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*
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* Clears reset signal to specified peripheral module, allows it to operate.
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*
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* @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
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* and reset bit position in the reset register.
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*/
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void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
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/*!
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* @brief Reset peripheral module.
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*
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* Reset peripheral module.
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*
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* @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
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* and reset bit position in the reset register.
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*/
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void RESET_PeripheralReset(reset_ip_name_t peripheral);
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#if defined(__cplusplus)
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}
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#endif
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/*! @} */
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#endif /* _FSL_RESET_H_ */
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